Hi Karthik,
I did the signal integrity study for parallel disk drive ATA33, 66, 100,
and 133. This was a parallel interface, source terminated into a 40 pin
ribbon cable and later an 80 pin ribbon cable. The number 33 refers to
33Mbytes/sec on a 16 bit wide bus.
First, the transmission line assumption commonly used is wrong when the
length is short (for ATA it was 18 inches). You can confirm that by
simply looking at the propagation time. The circuit is modeled by a
series tuned LC circuit where the line is an inductance and the load is
shunt capacitance.
Second, the inductance of the connection goes up when the loop area of
the signal and its return path increases. In ATA33 a 40 pin cable, did
not have many grounds so the loop area was relatively large. The source
series termination resistors were different values depending on the loop
area of the circuit in the cable.
In ATA100, we went from the 40 pin cable, to an 80 pin cable with ground
signal ground configuration. This reduced the loop area and thus the
inductance. I made a computer model for this cable which I used to
verify all the configurations used by our customers. The value of the
series termination resistor was based on achieving a damping factor of
0.7 which gives the fastest risetime in an RLC circuit--this is a
fundamental limit. We also specified a maximum load capacitance to get
the resonant frequency up, and thus the risetime shorter. The series
resistor value of 33 ohms was confirmed with extensive lab experiments
with 22 ohms and 51 ohms.
Using custom driver design we achieved a higher transfer speed for
ATA133, the limiting factor of other designs being the timing skew from
the drivers under loading so most implementations used the ATA100 speed.
To get to 1GHz speed, I used a different technique on a previous
design. It had a series terminated coaxial transmission line of 90 ohms
impedance and worked for a 3 meter distance. The voltage swing needs to
be lower than 5 or 3.3 volts, I used 1.0 volt swing to reduce the power
dissipation and ease the driver design. This meant the receiver had to
have sufficient gain to convert back to 5 volt swing.
I hope that answers your questions.
Regards,
Charles Hill
On 7/31/20 10:47 AM, John Ellis wrote:
For unterminated signaling to work you want the interconnect to be short------------------------------------------------------------------
enough to behave like a lumped load instead of a transmission line.
Impedance match of the driver is important. Coupling between signals is very
important in maintaining that impedance match since odd and even coupling of
signals can result in very different modal impedances that you're trying to
match with your driver. HBM2 is an unterminated parallel interface that
operates up to 3600Mbps. The route is about 5m typically but there are
applications that go to ~10mm. HBM3 is targeted to run at 6400 or 7200 in a
similarly routed interconnect. These are all point-point. If you routing
your CA as a Tee there will be additional challenges.
John Ellis
Principal Engineer
Mixed Signals &
I/O Libraries Group
Synopsys, Inc.
email: jellis@xxxxxxxxxxxx
Phone: 508.263.8194
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf
Of Scott McMorrow
Sent: Friday, July 31, 2020 11:38 AM
To: kchandr2@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [EXTERNAL]Si-List : Unterminated signaling
It depends. If the driver is close to being impedance matched to the line,
then a unidirectional point-to-point interface can be quite fast, as the
driver approximates a series terminator. Otherwise, your limit is the length
of the line w.r.t. the signal risetime and frequency of the data, and the
strength of the driver. In general, unterminated single-ended signaling
falls apart either when the interconnect length is greater than ½ the signal
rise time, or the interconnect length approaches one half of the signaling
rate.
YMMV
Scott McMorrow, CTO Signal Integrity Group Samtec Office 401-284-1827 |
+1-800-726-8329
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From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf
Of Karthik Chandrasekar
Sent: Friday, July 31, 2020 11:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [EXTERNAL][SI-LIST] Si-List : Unterminated signaling
Hi Experts
Wanted to know if anyone has experience in limits of unterminated
signaling in parallel bus designs (for example for CMD interface)?. What
is the highest speed one can do unterminated signaling at ?.
For e.g is 1GHz unterminated signaling possible ?
Regards
Karthik
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