It is possible to extract full s-parameters for signal, power and ground pins.
This requires an additional measurement reference plane for each local region (
for example, BGA vs. DDR module). You place a port between each signal, ground
and power pin and the plane.
Sent from Outlook Mobile<https://aka.ms/blhgte>
________________________________
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> on behalf of
Cristian Gozzi <cristian.gozzi@xxxxxxxxx>
Sent: Saturday, May 16, 2020 2:43:42 AM
To: wang1.1@xxxxxxx <wang1.1@xxxxxxx>
Cc: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
Subject: [EXTERNAL][SI-LIST] Re: how to use s-parameter to simulate power-aware
SI issues.
Which tool have you used for the extraction?
The main topic here is partial inductance vs loop inductance
When you extract the pdn and you use a full wave solver FEM based you will
get the loop inductance and loop resistance... means only ports for
positive terminal and the reference is a common ground
This doesnât mean your ground bounce is not taken into account, but simply
you cannot split power bounce from ground bound or dc drop in power rail
from dc drop in ground... everything is in a loop format...
If you want to have the 2 effects separated you have to use a different
extraction tool based on partial RL solver like most of the MoM tools do
In this case you will get a dedicated pin for the power rail and dedicated
pin for ground
Then you can look at power bounce and ground bounce separately because the
tool extracted the partial self inductance of power rail and the partial
self inductance of the Ground plus the mutual between the 2
Note: with this method do not connect each ground pins To common ground
otherwise you will short out the RL portions of your ground and you will
get an optimistic response
I hope this help
Cris
On Thu, May 14, 2020 at 10:14 AM TangH <wang1.1@xxxxxxx> wrote:
Hello everyone,
Recently i have a study about PI+SI co-simulation. I have extracted the
PDN and got the 3 ports S-parameter file. The port 1 for cpu power, port 2
for DDR power and port 3 for VRM. So in the schematic diagram (using ansys
designer) I connected port 1 and 2 to corresponding ibis-model's power pin.
When the simulation is done. I noticed that level '1' is much worse than
level '0'. In my schematic diagram design, each port is only one pin
visible and is is ref GND by default, and the ibis-model ref GND
too.It<http://too.It>
means all port's GND and ibis-model's GND is short, the current does'nt go
through the ground plane any more.
What should i do if i want to probe the ground's voltage in each port, and
see the impact of level '0'.
Thanks
Tangh
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