[SI-LIST] EMI, Package design and FPGA pinouts

From: "Bond, David" <David.Bond@xxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 1 Feb 2012 10:39:10 -0800

Hello SI Experts,
Can anyone point me to a good reference which deals with how to minimize
EMI thru silicon package design?   (i.e. not box design...)

 

Specifically, the areas of concern are that I have a large-ish silicon
die with a core clock speed >500MHz with many differential I/Os running
at 10Gbps in a flip-chip BGA (probably a 3-2-3 stackup).  My customer is
very concerned about the EMI of this device.  I'm looking for ways which
can minimize the EMI.  I've heard that the use of a grounded metal lid
is helpful; and that placing a ring of ground balls on the outer ring of
the package is helpful.  But these seem to be more qualitative answers
than quantitative.

 

Any pointers or suggestions would be much appreciated.

 

Thanks in advance,

-david.


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[SI-LIST] EMI, Package design and FPGA pinouts

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