[SI-LIST] 答复: Dynamic phase compensation in SERDES layout
- From: 蔡晓光 <xiaogcai@xxxxxxxxx>
- To: Istvan Nagy <buenos@xxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 16 Jan 2013 22:28:11 +0800
Hi, Istvan,
Thank you for your support!
So what you mean is the dynamic phase compensation has better common mode
performance. But there are would be most bump if we use tightly constraint. It
could make the differential impedance un-continued. So my second question is
how to define the DPS constraint? We must make come balance between the bump
and the skew.
Xiaoguang Cai
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å件人: "Istvan Nagy" <buenos@xxxxxxxxxxx>
åéæ¶é´: â2013/â1/â15 13:33
æ¶ä»¶äºº: "xiaogcai@xxxxxxxxx" <xiaogcai@xxxxxxxxx>; "si-list@xxxxxxxxxxxxx"
<si-list@xxxxxxxxxxxxx>
主é¢: Re: [SI-LIST] Dynamic phase compensation in SERDES layout
Hello,
Normally we would want along the whole length of the connection that the P
and the N legs have voltage at 180degrees phase difference. This way they
contain most of the signal energy in the pair and in the differential (not
common) mode. We dont like too much energy escaping (radiating away, or
propagating between the planes into other signals or reflecting back from
the plane edges and arriving back in the wrong time), and we also don't like
common mode stuff (mode transformation) arriving into the imperfect receiver
buffer. Also picked up common mode noise can be transformed into
differential signal in the unbalanced segment and appear as noise at the
receiver. So if there are longer segments where the 2 legs are unbalanced,
things go wrong there that cannot be reversed by re-matching them at the end
of the path (irreversible effects). The smaller the unbalance at the shorter
segment is the better.
regards,
Istvan Nagy
-----Original Message-----
From: Xiaoguang Tsai
Sent: Monday, January 14, 2013 6:59 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Dynamic phase compensation in SERDES layout
Hi, Experts,
I'm very curious that why the dynamic phase compensation(DPC)/running skew
compensation is necessary in high speed SERDES layout? And how the
parameters about the DPC are defined (
http://www.cadence.com/Community/blogs/pcb/archive/2010/11/03/what-s-good-about-differential-impedance-in-constraint-manager-see-for-yourself-in-spb16-3.aspx)?
Thank you very much!!
Xiaoguang Tsai
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