[SI-LIST] Re: Dividing a low jitter clock by 2
- From: "Alfred P. Neves" <al@xxxxxxxxxxxxx>
- To: "'Peter zhu'" <yonghui.sky@xxxxxxxxx>, "'Mikhail Matusov'" <matusov@xxxxxxxxxxxx>
- Date: Sat, 31 Jan 2009 13:43:47 -0800
Marc,
The phase noise drops 20Log(n), where n is the divider ratio, so the time
domain jitter reduces with a divider with everyone else equal. Using a
post divider is a good way to provide an A/D with a low jitter clock to
obtain close to theoretical Effective Number of Bits, ENOB.
I used a divider for one of my consulting projects several years ago,
reducing the jitter in an ATE environment, worked really well.
In my experience, simple digital systems don't add significant jitter to PLL
based clock sources, except when there is SSO, SSN, or termination and other
SI issues are not addressed.
Alfred P. Neves <*)))))><{
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Peter zhu
Sent: Friday, January 30, 2009 9:27 PM
To: Mikhail Matusov
Cc: SI-List
Subject: [SI-LIST] Re: Dividing a low jitter clock by 2
Marc:
As my experience, clock jitter is determined by the source clock. In theory,
simple sequential or combinational logic will no introduce jitter. In one of
our high-precise telecom clock board design, we use a low-jitter
temperature-compensate OSC, but we use a general CPLD to generate other
clocks with different freq. Keep an eye on using PLL, because your jitter
will be determinded by ths PLL after you clock go through this PLL.
Peter zhu
Emerson Network Power
On Sat, Jan 31, 2009 at 12:10 PM, Mikhail Matusov
<matusov@xxxxxxxxxxxx>wrote:
> Marc,
>
> You need to tell us what low means and you need to understand how much
> jitter you can actually afford. Besides jitter you have to consider clock
> skew you will be introducing.
>
> /Mikhail
>
>
>
> ----- Original Message -----
> From: "Marc Battyani" <marc.battyani@xxxxxxxxxxxxxxxxxx>
> To: "SI-List" <si-list@xxxxxxxxxxxxx>
> Sent: Friday, January 30, 2009 5:44 PM
> Subject: [SI-LIST] Dividing a low jitter clock by 2
>
>
> > Hello,
> >
> > I have a design with a low jitter reference clock at 50MHz. I would like
> > to divide it by 2 but without adding much jitter.
> > Can I do that with a $0.40 D flipflop gate or do I really need a low
> > jitter PLL?
> > I think the flipflop can degrade the cyclic ratio and add some unknown
> > delay but I don't see why it would degrade the jitter performance.
> > Am I to optimistic? The signals are 1.8V CMOS.
> >
> > Thanks,
> >
> > Marc
> >
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