[SI-LIST] Re: Digest Number 1151
- From: Shalini S <ssankarsin24@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 18 Jul 2004 20:16:08 -0700 (PDT)
Hi,
I was wondering if someone can tell me how can characteristic impedance of a
simulated PWB checked in HFSS.
Thanks
si-list@xxxxxxxxxxxxxxx wrote:
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There are 8 messages in this issue.
Topics in this digest:
1. Course on Signal Integrity at San Jose State University
From: "Ji Zheng"
2. Re: six layer, eight layer, other
From: "calaf_calaf_calaf"
3. spliting lvds clk
From: "Moshe Frid"
4. Re: spliting lvds clk
From: steve weir
5. Re: Differential pair via modeling
From: Ivan Ndip
6. Re: High Speed PCB design standards
From: Nick Paulter
7. Re: High Speed PCB design standards
From: Scott McMorrow
8. Re: High Speed PCB design standards
From: Nick Paulter
________________________________________________________________________
________________________________________________________________________
Message: 1
Date: Tue, 6 Jul 2004 18:59:35 -0700
From: "Ji Zheng"
Subject: Course on Signal Integrity at San Jose State University
I will be teaching a course "Engineering 242 - Electrical Requirements for
Microelectronic Packaging" this fall at San Jose State University. This is
part of the Packaging Program at San Jose State University and has basically
evolved into a course on Signal Integrity. The details of the course are as
follows:
Course Description:
As clock speeds increase in digital and communication circuits, Signal
Integrity has become very critical both on-chip and off-chip. This course
will deal with Signal Integrity issues in IC packages and Printed Circuit
Boards (PCBs). Starting with RC, RL, and RLC circuits, basic circuit
analysis will first be introduced. Partial Element Equivalent Circuit (PEEC)
as an important means of package modeling is then presented along with its
electromagnetic interpretations. Various kinds of drivers and receivers
using nonlinear circuit elements will be considered next followed by
interconnect modeling and phenomena related to transmission lines such as
reflections, delays, and crosstalk. Analysis and termination methods for
differential pair are also covered. Design of Power Delivery Systems (PDS)
and related topics such as Simultaneous Switching Noise (SSN) and decoupling
capacitor placement will next be described. Selected topics on the system
level simulation may include IBIS models for buffers, S-parameter models for
interconnection channels, as well as package characterization by EM solvers.
Measurements using Network Analyzers and TDRs will be introduced. The
circuit simulator SPICE will be used extensively. Where possible, public
domain EM solvers such as FASTCAP and FASTHENRY will also be used.
Prerequisites: Graduate standing; BS in engineering, chemistry or physics;
Consent of instructor.
Times: Aug 28 through Dec 18, 2004 (Saturdays) 9:00 a.m. - 12:00 noon;
Room: E301
Instructor: Ji Zheng, Ph.D., Sigrity, Inc. (email: zheng.ji@xxxxxxxx)
Enrollment Info: For those not enrolled in SJSU?s graduate program, this
course may be taken through SJSU?s Open University. The cost is
approximately $635 + cost of textbook for the 15 week course. For early
enrollment please contact the SJSU Continuing Education Office at (408)
924-2670. Enrollment during the first class period will also be
facilitated.
For further information contact: Dr. Guna Selvaduray at SJSU; Tel: (408)
924-3874; FAX: (408) 924-4057; email: gunas@xxxxxxxxxxxxxx
Best Regards,
__
/' _/ / _ _
(_// /__/)(-/)(/
_/
SIGRITY Inc. (www.sigrity.com)
4675 Stevens Creek Blvd. Ste.130
Santa Clara, CA 95051
Voice 408 260 9344 x 110
Fax 408 260 9342
Email jizheng@xxxxxxxxxxx
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Message: 2
Date: Tue, 06 Jul 2004 07:59:05 -0000
From: "calaf_calaf_calaf"
Subject: Re: six layer, eight layer, other
Hi,
I think others voltages planes are less important. The bottleneck is
that in a FPGA with BGA package, three voltages (3.3, 2.5, 1.2) live
together and are hard to separate in only two stack planes. Due to
this, I may need three different power planes, but for 1.2 V and 2.5
V, only a region placement below the FPGA footprint is required. The
only device, which uses those voltages, is the FPGA.
I wish I were able to confine these 3 voltages in only two planes but
I am afraid I might not get it and in that case I should use a 8
layer stack design
Thanks
--- In si-list@xxxxxxxxxxxxxxx, steve weir wrote:
> calaf, as to layer count there are various ways to estimate the
number that
> will be necessary assuming you have placement flexibility. If you
don't
> have placement flexibility it gets tougher. Six voltages can be a
bit
> challenging, especially if you can't concentrate each.
>
> Stack-up #1 doesn't look very good to me. It looks like an EMC
nightmare
> waiting to happen. It also looks unbalanced from a Cu standpoint
and will
> likely warp.
>
> Stack-up #2 is better, but still not very appealing. Without more
> information on just how much Cu you need for each of those five
voltages it
> is difficult to make a specific recommendation.
>
> Maybe if the fill balances out right:
>
> 1 signal
> 2 gnd
> 3 routed power, signal
> 4 3.3V plane
> 5 gnd
> 6 routed power, signal
> 7 gnd
> 8 signal
>
> Steve
> At 11:56 AM 7/5/2004 +0000, calaf_calaf_calaf wrote:
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Message: 3
Date: Wed, 7 Jul 2004 10:42:57 +0200
From: "Moshe Frid"
Subject: spliting lvds clk
hi all
I need to split diff clk of lvds at 800 MHz to 2 fpga that are far one
from the other
the data are in 8 channels ,4 to each fpga .
should I split them with buffers ? what about the delay of the clk
(the data would not be buffered)
tnks.
Moshe Frid
Adcom pcb design
Email:moshef@xxxxxxxxxxx
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Message: 4
Date: Wed, 07 Jul 2004 02:18:39 -0700
From: steve weir
Subject: Re: spliting lvds clk
Moshe, the right answer depends. Assuming that the distance difference is
not so much as to create a timing problem of its own due to differences
between clock and data physical lengths, then end terminate at the far FPGA.
With that said, 800MHz for the basic clock rate is pretty marginal for a
common clocked bus with FPGAs. If the FPGA design does not have a phase
adjustment mechanism it is very unlikely to work reliably under any
circumstances with any current production FPGAs. Current generation FPGAs
are only really able to trim phase to a resolution of about 250ps, and burn
up considerable resources doing so. The design engineer has some homework
to do.
Steve.
At 10:42 AM 7/7/2004 +0200, Moshe Frid wrote:
>hi all
>
>I need to split diff clk of lvds at 800 MHz to 2 fpga that are far one
>from the other
>the data are in 8 channels ,4 to each fpga .
>should I split them with buffers ? what about the delay of the clk
>(the data would not be buffered)
>
>tnks.
>
>Moshe Frid
>Adcom pcb design
>
>Email:moshef@xxxxxxxxxxx
>
>
>
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Message: 5
Date: Wed, 07 Jul 2004 14:30:49 +0200
From: Ivan Ndip
Subject: Re: Differential pair via modeling
Hi Doug,
here are some papers on differential via modeling.
Laermans, E., De Geest, J., et al.,"*Modeling Differential Via Holes",*
IEEE Topical Meeting on Electrical Performance of Electronic
Packaging, pp. 127-130, October 2000.
Abhari, R., Eleftheriades, G.V., van Deventer-Perkins, E., "*Analysis of
Differential Vias in a Multilayer Parallel Plate Environment Using a
Physics-Based CAD Model",* 2001 IEEE MTT-S, Volume 3, pp. 2031-2034.
Chen Wang, Jun Fan et al.,"*The Effects of Via Transitions on
Differential Signals",* IEEE Topical Meeting on Electrical Performance
of Electronic Packaging, pp. 39-42, October 2001.
Best regards,
Ivan Ndip
Doug Hopperstad wrote:
>Hi all,
>I am looking for some information on differential via modeling. The
>differential nets travel through via holes between non-adjacent layers.
>A return stitch is typically placed near the layer jump via to provide a
>return path for single-ended nets. With differential pairs, the
>common-mode signal would need a return path but I am not finding any
>information on how to calculate the anti-pad size, placement of the vias
>and return stitch for differential nets.=20
>
>I have been reading Howard Johnson's latest book on via modeling but it
>only talks about single-ended vias.=20
>
>Can someone provide a good reference source on this issue, thanks.
>
>Doug Hopperstad
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Message: 6
Date: Wed, 07 Jul 2004 13:49:49 -0400
From: Nick Paulter
Subject: Re: High Speed PCB design standards
I have a couple of comments regarding L. Ritchey's e-mail.
1. The IPC-2141A is not a standard, it is a guide, therefore, it is
instructional/informative and not normative.
2. "Rule of thumb" appears in 4 different paragraphs, regarding:
1. maximum number of signal pins per ground pin
2. when should a transmission line be considered a lumped or
distributed element
3. separation of signal conductors of controlled impedance lines
from ground/reference planes on the same plane
4. width of the reference plane relative to that of the signal line
3. "Rule of thumb," "common knowledge," "general rule," "common practice"
are all somewhat similar terms that have the purpose of providing guidance.
4. The members of the IPC working group (D-21c) that rewrote the IPC-2141
are experts in what they do. I doubt very much if these people would want
to have incorrect statements in the document.
5. The IPC-2141 was reviewed by experts outside of the D-21c.
I'm sorry if I wasted your time with this e-mail, but the unfortunate
comment may have inappropriately denigrated the work of the D-21c members,
which is not acceptable.
Regards,
N.G. Paulter, Project Leader
Pulse Metrology and Time Domain Measurements
Mail Stop 8172
National Institute of Standards and Technology
Gaithersburg, MD 20899
301-975-2405
At 08:16 AM 7/5/2004 -0700, you wrote:
>Unfortunately, this standard has an excessively large number of "Rules of
>thumb" which are not correct. I'd advise reading it with a great deal of
>caution.
>
>Lee W. Ritchey
>Speeding Edge
>P. O. Box 2194
>Glen Ellen, CA 95442
>Phone- 707-568-3983
>FAX- 707-568-3504
>
>I just used the energy it took to be angry to write some blues.
>Count Basie
>
>
> > [Original Message]
> > From: Nilesh Kawadkar
> > To:
> > Cc:
> > Date: 7/5/2004 3:03:30 AM
> > Subject: [SI-LIST] Re: High Speed PCB design standards
> >
> > Hello Vishnu,
> >
> > IPC-2141 is a standard developed by the institute for Interconnecting and
>Packaging Electronic circuits.This is a standard which i think will be
>helpfull to you.
> >
> > Other then this i have never come across any such standard for high speed
>PCB design.
> >
> > There are a lot of application notes,whitepapers and documents available
>on internet.
> >
> > Best Regards
> >
> > Nilesh Kawadkar
> >
> >
> >
> > vishnu.jwalapuram@xxxxxxxxx wrote:
> > Hi,
> > I am in hunt for buying some high speed PCB design standards.
> > I am ware of IPC standards.
> > Do anyone know any other design standards that are specifically meant
> > for High Speed Board designers ?
> >
> >
> > Thanks,
> > Vishnu
> >
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Other related posts:
- » [SI-LIST] Re: Digest Number 1151
