[SI-LIST] Re: Diff Pairs

  • From: "Charles Grasso" <cgrassosprint1@xxxxxxxxxxxxx>
  • To: <scott@xxxxxxxxxxxxx>, "silist" <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 5 Oct 2003 08:23:50 -0700

Scott,
thanks for soing this. I have a question though. I infer
that this a stripine broadside coupled pair?

How about a similar study for an edge coupled pair
ustrip configuration?


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
Sent: Friday, October 03, 2003 3:53 PM
To: silist
Subject: [SI-LIST] Re: Diff Pairs


All,
So, "just for fun"  I decided to run a differential pair trace through a
field solver and put some numbers to our musings on differential pair
loss vs. width and spacing.  As Lee Richey likes to point out, it is
always good to add a bit of actual science to our conjectures about
these things.

For this particular experiment I assumed FR-4 with an Er = 4.2 and a
loss tangent of .02, which is representative of some of the resent
designs we have built and measured here at Teraspeed.  The dielectric
width from plane to plane was kept at a constant 14 mils, and the
differential pair was constructed as stripline in the center of the
layer.  Finally, the pair width and spacing was adjusted from weak
coupling to tight coupling, always keeping differential impedance
constant at 100 ohms.  Here are the results for a frequency of 1.5625,
which is the Nyquist frequency for 3.125 Gbps binary data streams::

width    separation      height          routed   width          conductor loss 
dB/in
 dielectric loss dB/in   total loss dB/in        20"     30"









7.5      30      14      45      0.0958          0.1481          0.2439         
 4.878   7.317
6.79     13.89   14      27.47   0.0973          0.1481          0.2454         
 4.908   7.362
6.05     9.62    14      21.72   0.101   0.148   0.249   4.98    7.47
5.4      7.55    14      18.35   0.1052          0.1481          0.2533         
 5.066   7.599
4.82     6.25    14      15.89   0.1098          0.1481          0.2579         
 5.158   7.737
4.3      5.35    14      13.95   0.1147          0.148   0.2627          5.254  
 7.881
3.84     4.67    14      12.35   0.1197          0.148   0.2677          5.354  
 8.031
2.5      3.07    14      8.07    0.1406          0.148   0.2886          5.772  
 8.658

There are several things to note here:

1) Since impedance is kept constant, dielectric loss is constant.
2) As pointed out by others, as trace spacing becomes smaller, and trace
width becomes narrower, and conductor losses increase.
3) Loss is dominated by dielectric loss.
4) For long traces there is just a titch less than 20% improvement in loss
by using a 7.5 mil conductor vs. a 2.5 mil conductor, with constant
impedance.
5) Trace linear density is improved by greater than 550% by using a narrower
conductor.
6) A wide trace is easier to manufacture and has better impedance control
than a narrow trace.


So, as with all things in engineering, there are tradeoffs.  We can trade
off loss for density by changing the conductor width.  We can also trade off
manufacturability, since a narrow conductor with small space is harder to
produce and control.  We can trade off poor vs. good impedance control.  All
of these must be evaluated for any design.

One assumption that everyone makes is that loss is bad.  This is not always
the case.  Given a choice, I generally appreciate having a bit of conductor
loss in a design, as it tends to de-Q resonant circuits quite nicely.
Little things like package, connector, blocking capacitor and via
discontinuites can benefit from a bit of increased resistive loss.

If you require the density, close spaced, narrow width differential pairs
win hands down, at a slight sacrifice in loss performance.  The interesting
thing to consider will be the overall system performance.  Due to other
discontinuities, it may be that overall performance is actually improved by
a little additional loss here and there.


regards,

scott
(Who doesn't have a book.)

--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

More than that, it does not have any benefit.  Tight coupling of
differential pairs forces the traces to be narrower increasing the skin
effect losses.  Also, this tight coupling is going to result in good old
cross talk that actually degrades the edges.

How the notion of tight coupling of differential pairs as beneficial got
started is a mystery to me.  There are several references that show that
tight coupling is not beneficial, one of them is Howard Johnson's latest
book, at least one column he has written and my recently released book.

Lee Ritchey



>> [Original Message]
>> From: Duane Takahashi <duanet@xxxxxxxxxxxxxxxxxxxxxx>
>> To: <si-list@xxxxxxxxxxxxx>
>> Date: 10/2/2003 3:58:59 PM
>> Subject: [SI-LIST] Re: Diff.Pairs
>>
>> Hi Juergen:
>>
>> Aligning the stack up for the broadside coupled diff lines is expensive.
>>    You can do this, but it drives up the cost of the board.
>>
>> Duane
>>
>
>
>>> > Hi Juergen,
>>> > You can find lots of  application notes
>>> > especially with respect to process variation
>>> > on differential pairs here:
>>> >
>>> >
>>> > www.polarinstruments.com/support/cits/cits_index.html
>>> >
>>> > In particular this one may be of interest:
>>> >
>>> >
>>> > How measured impedance may vary from field solver calculations when
>>> > using woven glass reinforced
>>> > <http://www.polarinstruments.com/support/cits/AP139.html>laminates
>>> >
>>> > www.polarinstruments.com/support/cits/AP139.html
>>> >
>>> >
>>> > And this note:
>>> >
>>> > Copper thickness, edge coupled lines and
>>> > characteristic
>>> > <http://www.polarinstruments.com/support/cits/AP151.html>impedance
>>> >
>>> >
>>> > www.polarinstruments.com/support/cits/AP151.html
>>> >
>>> >
>>> >
>>> > Hope this helps....
>>> >
>>> >
>>> > Kind regards
>>> > Martyn Gaudion
>>> > www.polarinstruments.com
>>> > T: +44 1481 253081
>>> > F: +44 1481 252476
>>> > M: +44 7710 522748
>>> > E: martyn@xxxxxxxxxxxxxxxxxxxx
>>> >
>>> > ============================================
>>> >   Controlled Impedance & Signal integrity tools
>>> >   for the Printed circuit fabrication industry
>>> > ============================================
>>



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