[SI-LIST] Re: DesignCon Papers
- From: Steve Weir <weirsi@xxxxxxxxxx>
- To: rsefton@xxxxxxxxxxxxx, "'silist'" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 07 Feb 2005 23:31:29 -0800
Bob, it is all a matter of coefficients. While Larry's world is the
rarified space of beyond bleeding edge impedances, ( he can cite one spec
for 0.4mohms ). It is quite possible to break most PDS anywhere from the
VRM to the die. Large FPGAs provide a lot of opportunity for that as do TCAMs
For a feel of how many people suffer PI problems, one need only read
"EETimes" 12/20/2004 pp18. "When bad packages kill good pc boards". To
quote the article in reference to PI problems perceived as in-package:
"Ritchey says he's been flooded with calls and e-mails from board
designers. "I've got one on my desk right now where the design will have
to be scrapped." Even worse, said Ritchey, is the client in Fremont,
Calif., that went belly-up because of packaging problems-the whole company
is gone.
"The worst part of it." said Ritchey, "is that when people call me and it's
the problem I thought it was, I have to tell them they're dead. It's a
rotten job.""
Those quotes are all in reference to power bounce, a fundamental PI issue,
be it on the board or in the package.
The poster child of the "EETimes" piece is a nine month, $20 million dollar
fiasco at Mahi Networks attributed primarily to bounce. Lee represents the
problem as in-package, while the article cited the Director of hardware
engineering, Mr. Ramon Hecker describing the problem as board-level
"But test data showed severe ground bounce and power bounce on the board,
as well as performance problems related to the operation of the serdes
links in the system environment."
Whether the excessive bounce is in the PCB, or the package, it is a PI
problem. Mahi may not have died like that Fremont client Lee spoke of, but
$20 million and nine months has got to put on a lot of hurt.
There are any number of other casualties of power delivery problems out
there, so the problems are definitely quite real.
One FPGA manufacturer found that they were spending a lot of time
supporting customers who failed to account for LOW FREQUENCY surges. They
found that they were able to greatly reduce those efforts by recommending
use of large tantalum capacitors. Larry Smith is probably grinning,
because this is a topic that he drives home from time to time: The PDS
response really does begin at DC.
As to expensive tools, there is an awful lot that can be done with low-cost
and readily accessible tools. Whether those are enough is again a question
of coefficients. If one wants to take something to the edge of its
envelope, be it for design economy, or performance limits, the closer to
the edge the greater the need for rigorous analysis and verification. If
on the other hand, one is willing to either apply margin on their own, or
strictly follow well-defined and proven design guides, that can work
too. the middle ground is likely an ever more slippery slope. If you want
to make a board fail, try removing all of the bypass
capacitors. Alternately, just remove all the bypass capacitors from Vtt on
a DDR design and see what happens to your signal push-out. If you want to
hear war stories, many real case histories are out there.
On the PI side to see if you have anything to worry about, you can start
out with nothing more sophisticated than a spreadsheet and some
patience. If you have lots of margin and you can live with the cost, get
on with the implementation and make great products. If not, well start
doing a more refined analysis, or change the approach.
Best Regards,
Steve
At 09:39 PM 2/7/2005 -0800, Robert Sefton wrote:
>Dear list, especially the power integrity experts and pioneers at Sun,
>Teraspeed, et al -
>
>I've been a list member for more than five years now - rarely contributing,
>but religiously monitoring the dialogue. In the 15+ years I've been in this
>business I've been responsible for or at least been involved in dozens of
>large PCB designs. Over all of those designs I've seen maybe 4-5 signal
>integrity problems (where operation was affected), but I have never, ever
>seen a power integrity problem. Virtually all of these designs have included
>at least one FPGA, a processor, and SRAM and/or SDRAM. And several have
>included FPGAs plus ICs dissipating 20+ watts with SPI-4.2, SerDes, DDR, and
>other high speed interfaces.
>
>I'm a consultant, and I primarily work with small start-up companies that
>have no budget and no inclination for SI tools. (They'll spend many $100Ks
>or even $1Ms on IC tools, but won't spend a dime on PCB tools other than
>schematic entry and layout.) Probably half of the boards I've been involved
>with are prototype builds where schedule is paramount. With these I can
>rarely exert enough control to get the layout exactly like I want, and often
>the boards go out with serious reservations on my part. I always try to
>observe the prevailing guidelines expressed here and elsewhere, but I've
>seen boards go out with barely any copper left in the "planes" beneath large
>power-hungry BGA parts due to poor via placement and large anti-pads. I
>recently saw a board come back where a large Virtex-II FPGA would not
>configure. It was traced down to the fact that the core power islands under
>the BGA were were so sliced up that they were not connected to the core
>power VRM. The swiss cheese core power "plane" was re-connected to the +1.5V
>supply with a 4" blue wire through one via on the bottom of the board. Guess
>what - it worked like a champ.
>
>I'm not trying to be an ass here (I'll leave that to Chris C. :`)), but I'm
>really beginning to question the need for some or even most of the
>theoretical PI analyses espoused here. I can't believe that luck has made
>all of my boards work over the years, despite not having access to SI or PI
>tools of any kind. What I really think is going on is that there are very
>few designs that need the ultra-low-mOhm, highly-simulated, and
>highly-engineered power distribution methodologies that have been discussed
>here recently. I'll be damned if I can make a board NOT work due to how
>power is distributed.
>
>In the PI discussions on the SI-list I almost never hear power/current
>levels discussed. I'm sure that Sun cranks out boards with processor ICs or
>modules that draw 10s of Amps of core power, where detailed analysis of the
>PDS is critical. But what about us mortals who design run-of-the-mill FPGA +
>PowerPC + MAC, etc., type of boards? As I said, despite some brutally bad
>layouts, I have NEVER had a problem related to power distribution.
>
>I have two requests to the list:
>
>1. When espousing SI and/or PI practices, please be as specific as possible
>about when these practices are warranted, and more importantly, when they
>are not.
>
>2. I would LOVE to hear more detailed reports from the trenches (i.e. war
>stories) about SI and PI problems that were actually seen on real boards
>(not in simulation), and how they were fixed. This is something that is
>almost NEVER discussed amongst the regulars here.
>
>I have a strong sense that non-experts (like me) who monitor this list are
>buying into methods that may not apply to their designs and are therefore
>over-engineering (one of my least favorite things - I prefer to
>under-engineer and get away with it).
>
>All comments are welcome.
>
>Best regards,
>Bob Sefton
>
>
>
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