[SI-LIST] Decoupling model

From: "antonioccd" <antonioccd@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Thu, 18 Sep 2003 08:27:53 -0000

  Hi all,

   I am trying to select the optimum decoupling cap for a moderate 
current demanding memory IC. This device peak power consumption 
reaches 1.8 amps in only a few (4 to 6) nanoseconds.

   The following elements have been included in the circuit for 
modelling the structure:

   - Cap models from the manufacturer, it includes ESR, ESL, 
capacitance, etc
   - 16-layer via inductance (about 400 pH) for connecting IC and 
caps to planes.
   - IC (pulsed current source) simulating the IC current consumption.
   - IC internal inductance (about a few dozens of pH)
  
   The PCB includes two adjacent planes (gnd-vcc) for high-freq 
decoupling whose L and C I am not sure how to model.

   Obviously, the memory manufacturer does not provide any model for 
the power pins of the IC, so I think this point could be another 
problem.

   Thanks in advance.

   Antonio.

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[SI-LIST] Decoupling model

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