[SI-LIST] Re: Decoupling capacitors selection
- From: steve weir <weirsi@xxxxxxxxxx>
- To: chundi srikanth <chundis@xxxxxxxxx>
- Date: Mon, 01 Feb 2010 01:27:10 -0800
Sree, there is no pat answer. Books have been written on this. If you
think that the evaluation board is physically representative of your
application: You are going to copy it's stack-up and power layout, and
you are going to exercise the chips the same on your board almost the
same as on the evaluation, and you are confident that the evaluation
board is reliable across your application environment, then you can copy
that implementation. Otherwise you have work to do that companies like
Sigrity or Mentor would love to assist you with by selling you $50K of
software per seat.
To intelligently address your question, for power delivery only you
would want to know the impedance profile versus frequency required at
the chip attachment to the PCB. Then you could apply some physics and
electrical engineering to meet that set of requirements.
To answer your question for signal returns, you need to know the spectra
and amplitude of the return currents that must traverse your PDN. Then
again you can apply some physics and electrical engineering to arrive at
an answer.
If you need to learn what to do yourself, and want to learn to do it
properly you can begin with:
Istvan Novak's website: www.electrical-integrity.com
<http://www.electrical-integrity.com> has a number of papers and book
links.
You would do well to read almost anything on the topic written by Dr.
Bruce Archambeault.
Xilinx offers "cookbook" power delivery network specifications for the
Virtex 5 and later FPGAs. It is useful, but deserves some caution and
won't tell you a thing about your processor, DACs, ADCs etc.
Finally, there are also a number of papers and book links at our web
site: www.ipblox.com, as well as application notes on the X2Y web
site: www.x2y.com.
Steve.
chundi srikanth wrote:
> Hi Friends,
> Iam little bit confused in the selection of right decoupling capacitor for
> my application. Iam using Freescale Coldfire MCF5208 processor. The
> processors core is running at 166.66MHz and its Memory bus is operating at
> 83.33MHz. In my board i have a Virtex-5 FPGA for CPRI protocol and
> interfaces to high-speed DAC, ADC. And i have a RF circuitry also. So my
> question is Whats the main criteria for selecting decoupling capacitors for
> this processor?Is there any formula to calculate the capacitance for this.
> Please give me your suggestion on this. And shall i keep a capacitor per pin
> or otherway?
>
> And i have seen the MCF5208 processor evaluation board which theye are using
> in Zigbee environment but they have placed very few caps of 0.1uF. Nothing
> else. Can i follow the same?
>
> Thanks & Regards
> Sree
>
>
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--
Steve Weir
IPBLOX, LLC
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Reno, NV 89501
www.ipblox.com
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