[SI-LIST] Decoupling Capacitors
- From: "Gareth Baron" <Gareth.Baron@xxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Apr 2004 15:41:47 -0700
We're trying to determine how many decoupling capacitors are needed for =
our
boards. I hear conflicting stories about using the power planes as
decoupling vs. using lots of different values of capacitors to give a =
spread
of low impedances presented to the pins or the ICs'.
Does anyone have any good advise (experimental/empirical or just plain
knowledge) on how I should go about designing our layouts with =
decoupling in
mind ? Any golden rules ?
BTW, I do not have buried vias in my arsenal of Engineering tricks. =
However
I can go down to 0402 footprints if needed.
TIA,
Gareth
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
