[SI-LIST] Re: Decoupling Cap. Strategies.
- From: Zhangkun <zhang_kun@xxxxxxxxxx>
- To: kedar.apte@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 19 Jan 2006 13:46:58 +0800
Dear Kedar
The following is my advice.
1.up to 150MHz
The decoupling capacitor is important. The fanout should be careful. Via in
pad is very good. However we seldom use this kind of technique. I think the
separation between the two vias should be cared because it will determine the
ESL.
2.150MHz to 500MHz
Maybe the embedded caps should be applied. The anti-resonance between the
discrete caps and embedded caps should be cared. In our boards, there is the
similar situation, that at some frequency, the noise in embedded PCB is larger
than that in the common PCB.
3.above 500MHz
There is nothing to do with the PCB:(
Hope this is helpful.
Best Regards
Zhangkun
2006.1.19
----- Original Message -----
From: "Kedar P Apte" <kedar.apte@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, January 19, 2006 1:17 PM
Subject: [SI-LIST] Decoupling Cap. Strategies.
> Hi All Gurus,
>
> What are the different decoupling capacitor placement and routing
> strategies for high speed boards...?
> If you specifically make a band of high frequencies like
> 1. up to 150 MHz.
> 2. 150 to 500 MHZ
> 3. 500 MHz and above.
>
> I can understand that for 50MHz and above designs every thing will be cross
> calculated and possibly simulated before finalizing.
>
> I just want to ask that for any design the strategy of putting a via to a
> power plan directly on the Capacitor Pad will work fine...? or there has to
> be some calculation and evaluation of the decoupling strategy for every
> design.
>
> Please if anybody can suggest any guidelines or documents it will be very
> helpful.
>
> I am getting many things on the net also and getting guideline documents
> from the chip manufacturers as well but a good discussion will always help
> me to finalize my strategic goal.
>
> Thanks & Regards,
> Kedar
>
>
> http://www.patni.com
> World-Wide Partnerships. World-Class Solutions.
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