[SI-LIST] Re: Dear, can anybody tell me what's the max overshoot and min undershoot value of PCI? thank you!
- From: "Ingraham, Andrew" <a.ingraham@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 22 Jul 2004 11:32:13 -0400
> can anybody tell me what's the max overshoot and min undershoot value of
> PCI?
There is no limit on the overshoot voltage.
(I use "overshoot" to mean the greatest excursion in both directions, so the
falling edge has an overshoot that goes negative. This is the IEEE
standard, but Intel and some others prefer to call it "undershoot" even
though undershoot means something else in the IEEE standard definitions.)
Although the overshoot voltage is not bounded, the PCI specs have a "stress
test" that you can apply to your circuits, to make sure that they can
withstand what is expected to be the worst-case overshoot conditions on any
real bus. This test is a combination of voltage and current (assuming that
your circuit has internal clamps that shunt some of the overshoot voltage).
Many people misunderstand the stress test because the open-circuit voltages
are so large (+11 Volts and -5 Volts or so, for the PCI 5V signaling
environment). But these are the open-circuit voltages only, and are
expected or required to be significantly less than this at your IC pins.
PCI also has a spec on minimum clamp current vs. voltage, and that would
limit the overshoot voltage. The stress test is as much a test of clamp
diode current, as it is of overshoot voltage.
+11 Volts was probably chosen because a rising edge signal might start
slightly negative (due to bus noise) then switch initially to Vdd(max) =
+5.25V. Upon reaching the ends of the bus, this initial wavefront could
double to about +11V, were it not for any clamping or impedance there.
But the +11V in the test circuit is behind a Thevenin equivalent source
impedance, so in practice it won't be that much voltage at your IC pins.
Regards,
Andy
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