[SI-LIST] Re: Data bus skew
- From: James_R_Jones@xxxxxxxx
- To: nitinbhandari@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 9 Jul 2002 18:26:21 -0500
Nitin,
A few of questions about your TDR measurements that may provoke thought:
What is the internal timebase jitter of your TDR? Are you measuring its
error?
How well in phase are the excitation pulses of the TDR?
Is this an inner, or an outer layer... soldermask thickness an issue?
How close are the return current paths for the layer transitions?
How thick is the board, and how much length mismatch is introduced going
into the board from the connectors and also vias?
How much swiss is in your planes?
Are your traces capacitively coupling to vias in the BGA field?
I have never tried to match so closely, but these were the first thoughts
that came to my mind.
Hope this helps,
James R.
-----Original Message-----
From: nitin bhandari [mailto:nitinbhandari@xxxxxxxxxxx]
Sent: Tuesday, July 09, 2002 5:39 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Data bus skew
I am working on a source sync interface that allows for only 20ps skew
between various data bits in a bus. I built a test board (i'm glad i did) to
conduct a feasibility study. I am puzzled at the finding and am hoping that
someone can shed some light on it.
first, some background:
Dielectric is Nelco-13.
Trace width is 4 mils.
All traces are 8000 mils (+/- 50 mils) long.
All traces are on the same layer and are referenced to the ground plane.
All traces have SMA connectors on one end and a BGA chip on the other. For
the purpose of this study, the BGA is not stuffed on the board. So, all
traces end in an open circuit.
All traces have equal number of vias.
There is minimal switch-backs on all traces (with 5X spacing).
When i TDR the traces, i find that the skew between the traces can be as
much as 100ps. I am careful to de-skew the TDR channels and cables+SMA
connectors.
Has anyone seen this type of behavior on PCB traces. Can different portions
of the board have different velocity.
Can anyone suggest any experiments to debug this problem.
Thanks in advance,
Nitin
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