[SI-LIST] DDR4 Logic Level
- From: icer world <icermail@xxxxxxxxx>
- To: SI LIST <si-list@xxxxxxxxxxxxx>
- Date: Thu, 28 Nov 2013 23:44:11 -0800 (PST)
Hi Experts,
It seems that input logic level VIH(AC)&VIH(DC)&VIL(DC)&VIL(AC) are not given
out in the latest JEDEC Standard.
Whether this means that it's needed to define them by ourselves at current
moment?
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