[SI-LIST] Re: DDR3 termination modes during READ and WRITE operation?
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: mik.nazaryan@xxxxxxxxx
- Date: Fri, 18 Jan 2013 08:43:52 +0100
Hi Mik,
this Termination during read refers to a multi rank System. So the DRAMs
on one rank are driving, while the DRAMs on another rank and the
Controller are terminating (and only the controller is receiving).
You will find quite a lot of pictures on terminations schemes for
Read/write in different configurations when searching for e. g.
application notes (guess this table is not in the specs as it is just a
guideline, but I would need to check on this one).
if you have a single rank solution you might want to switch on a light
termination on the DRAM during write (e. g.60 or even 120ohm) and a
reduced DriveStrenght (e. g. 48 ohm). For the writes you would select
low drive strengh on the DRAM and also a light termination on the
controller.
but this is just guessing. It really depends on the chips you are using,
your board layout and the configuration.
Your have several options:
- You can just set something and if it works cross your fingers that
this is providing enough margins and is not violating the spec during HVM
- You can simulate and optimize the Termination and drivestrengh (hoping
that the Controller really hits the programmed values)
- You can measure and confirm the simulation and signal integrity
(preferred solutions).
Best regards
Hermann
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Am 18.01.2013 08:13, schrieb Mik Nazaryan:
> Hi friends,
> Currently I'm tiring to solve the SI problems between DSP and DDR3
> memory and I need some help to clarify the situation.
> Suppose we have one DPS chip and DDR3 memory.
> There are possible different type of termination methods for SSTL15 I/O
> cell in DSP chip and in DDR3 memory.
>
> 1. ODT (20,30,40,60,120Ohm), - ODT and Dynamic ODT,
> 2. Output impedance (Z0=34, 40, 48Ohm), Same as OCT?
> 3. Pull up,
> 4. Pull down,
> 5. Open mode,
> 6. PWRDWN,
>
> To solve SI problems in this system, we have opportunity to choose I/O
> cell (if DQS/DQSQ this is PDIFF cell) modes from both sides. ( for
> example in WRITE mode: from DSP side series termination, from DDR3
> memory side ODT).
> According to the JECED the DDR3 can not terminate with ODT and drive at
> the same time. But I have read couple of articles where even during read
> mode ODT enabled from memory side.I am already confused. My question is,
> which of these terminations are possible to combine together during
> write and read operation?
>
> Thank you.
> Mik
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