[SI-LIST] Re: DDR3 route trace maxim length
- From: "Marc Humphreys" <mhumphreys@xxxxxxxxxxxxxxxxxxx>
- To: <emcesd@xxxxxxx>, <msrajesheee@xxxxxxxxx>
- Date: Fri, 26 Oct 2012 00:48:46 -0400
Got 10-12 inches running at 800Mhz (1600Mbs), but that's with a controller
that can train and deskew per bit.
Marc
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Tesla
Sent: Friday, October 26, 2012 12:38 AM
To: msrajesheee@xxxxxxxxx
Cc: lipishang@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR3 route trace maxim length
Hi,
I think only the chip system designer can answer this question. there are
too many viariables, the root problem is timing.
With long PCB trace, you get more ISI,crosstalk,weave effect.......
BTW, why put DDR memory chip far away? Good practice always give good yield.
Thanks.
Tesla
At 2012-10-26 02:07:10,"Rajesh Kumar" <msrajesheee@xxxxxxxxx> wrote:
>Hi Pishang,
> It depends on the driver strength, trace parasitic
>Timing problem will be rectified as far as you route your traces in
>equal length (refer datasheet of any DDR for timing and tolerance).
>
> Maximum trace length will be specified by SOC vendors
>if you are using any SOC. Good termination schemes will avoid
>reflections due to lengthy traces.
>
> Try to do some simulation with with model of driver and
>DDR for different trace lengths to find out the real value.
>
>Thanks,
>Rajesh
>
>On Wed, Oct 24, 2012 at 11:57 PM, shuang wu <lipishang@xxxxxxxxx> wrote:
>
>> Hi Experts,
>>
>> I have a question is that :
>>
>> How long we can route the DDR3-1600 trace on FR4 if the topology is
>> point to point (One Controller connnected with one memory )?
>> Maybe we need to consider SI and timing problem .Have anybody cover
>> this before?
>>
>> --
>> Br,
>> pishang
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>
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