[SI-LIST] Re: DDR3 Reset line
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 12 May 2010 10:08:01 +0200
Hello,
from a DRAM point of view the Reset signal should be totally independent
of the CLK and absolutely asynchronous.
I do not see a reason for any dependency between clock to reset. I did
a short check on UDIMM, and did not find any timing relation considered
there.
I also do not see any need for the controller, as after a reset it has
to do some init steps anyhow.
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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94554 Moos
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schrieb Lee Isaac:
> Hello All,
> On DDR3, is there any skew constraint between the clock and the reset line.
> The reset line is asynchronous but I have seen a DDR3 controller which
> specifies a constraint to the clock.
> Would there be any need to limit the skew between clock and reset?
>
> Thanks
> Lee
>
>
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> ..............................................................................
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