[SI-LIST] Re: DDR3 PCB trace spacing
- From: Michael Greim <mgreim001@xxxxxxxxx>
- To: julialiu.si@xxxxxxxxx
- Date: Tue, 13 Nov 2012 22:46:16 -0500
I am still sticking with my thumbs down to rules of thumb, or
thumb down to folks who say I did it this way because they
told me to do it this way. (unless of course I am being brought
in as a consultant to fix it......;-) )
Not sure where 5% came from in Erics book but was that for
every signalling interface or just DDR3? Sounds like that is
a question for him.
I would wager that your memory controller mfg has the answer
to a great many of your questions. Insight into the speed and
power variant of your DDR3 channel population will probably
have quite a bit to do with your answer.
Then there is the ole how hard do you want to push the margin
wall vs route densty and board cost? All real questions.......
So the answer to your spacing question is.........It depends.
-Michael.
We will either find a way or make one - Hannibal
In the middle of every difficulty lies opportunity - Al Einstein
If you think you can do something or you think
you can't, in both cases you are probably right - H Ford
If you're not getting the results you want with the
current approach, move on and try something else. - A. Fleischmann
On Tue, Nov 13, 2012 at 7:30 PM, julia liu <julialiu.si@xxxxxxxxx> wrote:
> Hi All,
> I am trying to answer a simple question, what is the right trace spacing.
> But when I start to work on this question, I found that it is quite hard to
> solve.
>
> This is what I think. Since I want to know trace spacing, Xtalk is the only
> factor that can be affected by trace spacing. Further, Xtalk amplitue is
> limited by Vih/Vil and timing budget. As a result, I need to simulate my
> system to pass timing and voltage noise requirement wihile changing
> spacing.
>
> Here are the questions that I have.
> 1. Should AC or DC Vih/Vil be used?
> When I compare voltage noise from Xtalk, I can compare to either AC or DC
> spec. Using AC spec will guarantee system work, but it is too conservative
> and left too little margin. Using DC spec may not meet AC spec.
>
> 2. How to create worst condition?
> DDR3 system is not 50Ohm. Driver, PCB trace and receiver all have different
> impedances. Xtalk and reflection worked with each other. With certain PCB
> trace length, it will create the worst timing or voltage noise. It is a big
> head for me to calculate the worst case trace length.
>
> 3. when simulating Xtalk, should I include package coupling, except PCB
> trace coupling?
> I think that the timing data from vendor data sheet already include package
> Xtalk. But Vih/Vil data does't include package Xtalk. Please correct me if
> I am wrong.
>
> I checked the package model S parameter. Controller's package has -30dB
> (~3%) @1GHz Xtalk. Controller's package has less reference gnu/pwr, which
> has relative larger Xtalk.Dram's package has -39dB (~1%) @1GHz Xtalk. DRAM
> package has good power/ground reference, whose Xtalk is not large.The via
> Xtalks in my PCB also have simliar number. -30dB for controller bias and
> ~40dB for Dram vias. All of them together is about 8%. This 8% seems not
> too small to be ignored.
>
>
> I read Eric's book. In his book he talks about give 5% of signal swing to
> Xtalk. He didn't mention whether this 5% is for PCB trace only. I think
> that it is. If I just use this rule of thumb number, the problem will be
> simplified greatly.
>
> Please let me know what is the right way to answer this simple question.
>
> Regards,
> Julia
>
>
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