[SI-LIST] Re: DDR2-1066 Input Slew rate measurement - reference levels question
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: Eugene Ivanov <eugene.ivanov@xxxxxxx>
- Date: Sat, 16 May 2009 10:34:58 +0200
Hi Eugene,
this inconsistancy comes from the change of the AC levels for
different speedgrades. While the AC level was adjusted for higher
speedgrades > 533Mb/s from 250 to 200mV there was no change for the
clock levels. I guess, because there was not seen any issue to reach
this level for the clock signal (very low load and steady state signal).
I did a short check on the measurement definition.
Samsung and Qimonda spec use the JEDEC definition from Vref to the AC
level to measure slew rate.
But when Downloading the Datasheet from Micron, for the MT47H64M16 i
got the message this is an obsolete product.
Then I was looking into the Definitions on the slew rate (figures 22
and 23 on pages 59) and this mentiones the JEDEC definition (Vref to AC).
As far I remember the original discussion in JEDEC was to use DC to
AC. So maybe this is an inconsistancy just not updated for an obsolete
product.
Regarding the discrepancy in the differential voltage levels 400mV vs.
500mV. I personally would use the number from the table, not from the
explanation.
I guess this is the one where Micron would say to be the relevant number.
Overall when you are going to discuss some topics like this with the
vendor, he will tell you the numbers in the Datasheet are the one he
guarantees. Neverteheless I'm sure, that you will not run into trouble
with the lower JEDEC numbers. But if you are having any other trouble
with your system and tell the vendor the DRAM is getting only the
lower numbers the vendor might say: First fix this problem to make
sure that this is not your real problem!
The question for me would be: are you really running into trouble with
the AC clock levels ? It should be easy to fix this ...
You are welcome to drop me a note if you are interested in some
offline discussion!
Regards
Hermann
--
EKH - EyeKnowHow
Hermann Ruckerbauer
www.eyeknowhow.de
hermann.ruckerbauer@xxxxxxxxxxxxx
Veilchenstrasse 1
94554 Moos
Tel.: +49 (0)9938 902083
Mobile: +49 (0)176 45 17 56 56
Fax: +49 (0)721 15 12 58 230
Eugene Ivanov schrieb:
> Hi all, I'm confused with the reference levels to be used for a
> DDR2-1066 input signal slew rate measurement. Micron datasheet
> seems to be different from JESD208 spec. What levels do you guys
> use to make sure the controller complies to the spec?
>
>
>> From JESD208
> General Note 2 Slew Rate Measurement Levels b) Input slew rate for
> single ended signals is measured from Vref(dc) to VIH(ac),min for
> rising edges and from Vref(dc) to VIL(ac),max for falling edges.
> For differential signals (e.g. CK - CK) slew rate for rising edges
> is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV
> to - 500 mV for falling edges).
>
> Micron MT47H64M16 datasheet in AC Input test conditions notes
> (p.55) states 4. The slew rate for single-ended inputs is measured
> from DC level to AC level, Vil(DC) to Vih(AC) on the rising edge
> and Vil(AC) to Vih(DC) on the falling edge.
>
> and gives more explanation how the dif input signal slew rate
> measured 9. The slew rate for differentially ended inputs is
> measured from twice the DC level to twice the AC level: 2 × Vil(DC)
> to 2 × Vih(AC) on the rising edge and 2 × Vil(AC) to 2 × Vih(DC) on
> the falling edge. For example, the CK/CK# would be -250mV to +500mV
> for CK rising edge and would be +250mV to -500mV for CK falling
> edge.
>
> But Vih(AC), Vil(AC) for DDR-1066 are Vref +/- 200mV, so the levels
> should be -250mV to +400mV for rising edge and +250mV to -400mV for
> falling edge, not 500mV.
>
> Thanks
>
>
>
>
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--
EKH - EyeKnowHow
Hermann Ruckerbauer
www.eyeknowhow.de
hermann.ruckerbauer@xxxxxxxxxxxxx
Veilchenstrasse 1
94554 Moos
Tel.: +49 (0)9938 902083
Mobile: +49 (0)176 45 17 56 56
Fax: +49 (0)721 15 12 58 230
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