[SI-LIST] Re: DDR2 spacing rule
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: "balaseven@xxxxxxxxx" <balaseven@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 29 Jul 2013 05:17:00 +0000
Bala,
One reason for the larger spacing between byte lanes is that byte lanes can be
routed at different lengths and
there can be significant phase offset between byte lanes. Not so much in DDR2,
but certainly in DDR3. Out of phase
xtalk is more problematic that xtalk within a byte lane. Since there are only
7 boundaries between byte lanes its
common to allocate more spacing to these boundaries in order to avoid or reduce
out of phase xtalk.
Brian Moran
Memory Interface Technology
Client Platforms
Intel Corporation
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of bala
Sent: Sunday, July 28, 2013 2:25 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 spacing rule
Hi All,
Why data lines of same byte in ddr2 routed together?As we know all the data
lines in a DDR2 running at same frequency and if we route byte0 and byte1 at
same length,why do we need to maintain different trace-trace spacing for same
byte and different byte?
--
bala
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