Hi Experts, For a new PCB design using two 16-bit DDR2 chips running at 250 MHz, the trace length increased from 1.5" in previous design to 2.0". Also, because of reduced card space, the traces had to be routed closer. This resulted in increase in crosstalk. The worst case crosstalk increased to about 220 mV, about twice compared to previous design. The design still seems to work fine. I made worst case crosstalk/noise measurements on the worst bit (31 bits switching High/Low, with this one bit quiet), which showed an amplitude of about 400 mV. Next I measured the noise on another bit, which had zero simulated crosstalk. This measurement showed about 170 mV of noise. The worst crosstalk happens when DRAMs are driving the bus. Can I assume that 170mV noise is entirely due to SSN/voltage ripple. In the next card revision, I have managed to get additional card space for placing series terminations and also spreading the traces. So now worst simulated crosstalk is about 100 mV. The ASIC manufacturer says that the crosstalk amplitude of up to 350 mV should not cause any problem. I am curious as to how much total noise will be acceptable in a DDR2 interface. Thanks for your help. Regards, Ravinder Ajmani Server PCB Development Hitachi Global Storage Technologies Email: Ravinder.Ajmani@xxxxxxxxxxxxxx ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu