[SI-LIST] Re: DDR2 - 7 LOADS -suitable topology

  • From: bala <balaseven@xxxxxxxxx>
  • To: "Zabinski, Patrick" <zabinski.patrick@xxxxxxxx>
  • Date: Tue, 20 Dec 2011 19:40:28 +0530

Mani,
Do you really need 7 DDR2..can u explain a bit about your
project/application...I dont think 7 DDR2 is needed.

Thanks
bala
SI Engineer,

http://www.facebook.com/Bala.The.Signal.Doctor

On Tue, Dec 20, 2011 at 7:08 PM, Zabinski, Patrick <
zabinski.patrick@xxxxxxxx> wrote:

> B.K.,
> A 7-drop daisy chain is challenging to properly terminate.  As mentioned
> in a previous post, it's useful to learn from what folks have previously
> done in DIMM packaging.  However, there are situations that fall outside
> of DIMM packaging that require custom solutions.
>
> One approach we found to be effective is to insert series resistors
> before each load - at the junction between the primary daisy-chain path
> and the load path.  The additional resistors (typically between 10 ohms
> and 20 ohms in value) help significantly, but they do increase the part
> count (i.e., cost).
>
> The values of the termination resistors and transmission lines need to
> be optimized for the particular application.  However, using
> optimization routines (often built in to your simulator, such as HSPICE
> and ADS) allow you to quickly determine useful values.
>
> It's a bit old, but we presented such a concept back at DesignCon 2007
> (TP1-10).
>
> Good luck,
> Pat Zabinski
>
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> > Behalf Of Balamanikandan K
> > Sent: Tuesday, December 20, 2011 5:19 AM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] DDR2 - 7 LOADS -suitable topology
> >
> > hi
> > A processor has to be connected to  7 DDR2 chips.What are the various
> > methods to connect them to achieve better signal integrity? What is
> the
> > alternative solution to achieve the symmetric topology?
> >
> >
> >
> >
> >
> > --
> > Best Regards,
> > Balamanikandan.K
> >
> >
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-- 
bala


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