[SI-LIST] Re: DDR1 without VTT termination
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Kathiresan K <k.kathir@xxxxxxxxx>
- Date: Mon, 31 Mar 2008 07:46:39 -0700
Kathir,
As long as your processor swings around VCCIO/2 you can make your
signaling levels. W/ series resistors in the middle only and traces
that aren't too long you can probably make 320Mbps timing. Resistors at
both ends for DQ will buy a little more margin than resistors in the
middle only. But if you are going to do that it begs the question of
why you don't generate VTT and do it per spec.
I would still terminate the DQS lines. Thevenin w/ short stubs s/b good
enough.
Steve.
Kathiresan K wrote:
> Hi,
> I need to have a single chip DDR1 (160 MHz, 16-Bit) memory for a processor.
> I don't want to provide VTT terminations. I'll keep the trace length as
> minimum as possible. I may provide series termination but I haven't done
> pre-layout simulation yet.
> Can somebody please clarify whether it can be designed without VTT
> termination? If yes, what can be the maximum trace length I go for? If I'm
> providing series termination, should I provide at both the ends for
> bi-directional signals?
>
> Regards,
> Kathir
>
>
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