[SI-LIST] Re: DDR via crosstalk
- From: julia liu <julialiu.si@xxxxxxxxx>
- To: "Carrier, Patrick" <Patrick_Carrier@xxxxxxxxxx>
- Date: Fri, 2 Nov 2012 12:51:10 -0700
Hi Patirck,
Thanks for the answer. The via coupling I mentioned about is in the BGA
field. I didn't make it clear in the first email. I believe that in BGA
field there is no space to add stitching vias.
Do you have any comments about BGA field vias about my original questions?
Regards,
Julia
On Fri, Nov 2, 2012 at 12:25 PM, Carrier, Patrick <
Patrick_Carrier@xxxxxxxxxx> wrote:
> Hello Julia--
> Via-to-via crosstalk for single-ended vias is highly dependent upon the
> stitching vias and stitching capacitors that connect the planes together.
> In fact, the characteristics of the signal vias themselves depend on
> stitching vias and capacitors. In other words, the return path of the via
> is made up of the board power distribution network (PDN), which consists of
> vias, caps, power planes, and any traces that connect them.
>
> To limit via-to-via crosstalk, you should have at least one transition via
> or capacitor (depending on whether the signal reference changes between
> planes of different potentials) by each signal via. It is usually easiest
> to do all via transitions right by the ICs, which tend to have large
> numbers of power and ground vias and caps nearby. But if you have to
> transition elsewhere, be sure to add appropriate numbers of stitching vias
> or caps. If multiple signal vias have to "share" their return path through
> the same stitching via, it can dramatically increase your crosstalk.
>
> You can use HyperLynx with the PI-integrated via model to calculate such
> crosstalk.
>
> Contact me directly or your local Mentor salesperson if you need more
> information.
> Additionally, you may find the following blog and referenced article
> useful:
>
> http://blogs.mentor.com/hyperblog/blog/2011/11/02/via-modeling-what-do-i-really-need/
>
> --Pat
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of julia liu
> Sent: Friday, November 02, 2012 1:52 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR via crosstalk
>
> Hi All,
> I am simulating Xtalk of DDR interface to give PCB trace spacing
> guidelines. I found that most EDA tools' support of Via couple modeling is
> not good.
>
> My question is:
> When designing DDR interface, is via coupling a significant enough portion
> of Xtalk that need to be considered?
> How much percentage of Xtalk is from via? (I know that this answer could
> be depends on the layout, but I want to get a rough idea) What EDA tool is
> easy to use to simulate hundreds MHz data rate via coupling?
>
> Thanks,
> Julia
>
>
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