[SI-LIST] Re: DDR stubs and non- stuff options

  • From: "Doug Brooks" <dbrooks7@xxxxxxxxxx>
  • To: "ranjith" <hw_si@xxxxxxxxxxxxxx>
  • Date: Thu, 7 May 2009 07:39:21 -0700 (PDT)

Think in terms of the "critical length." You don't say what the rise time
of the clock is, but at 133MHz the critical length is likely not less than
1.5" to 2" (quite likely more). Thus, .1" is such a small fraction of the
critical length that the stub reflections will not be an issue.

Doug Brooks
http://www.ultracad.com



> Thanks for the feedback.
> We are using mobile DDR. The Maximum clock frequency is 133MHz.
> While routing dasisy chain, we are estimating 100 mils stub in DDR(1)
> which close to the processor (see below diagram). If we no mount this
> DDR(1) this 100 mils additional stub will be there. Is this stub will
> create an issue in 133MHz DDR operation?
>
>       TLA = 1"      stub = 0.1"
> CPU ----------------o------- DDR(1)
>                     |
>          TLB = 0.7" |
>                     |
>                     |
>                   DDR(2)
>
> Thanks
> Ranjith
>
>
> Stubs are never a good idea.  Whether your stubs will be enough to wipe
> out your margins depends on how fast you intend to signal and what your
> layout looks like.  You should arrange your layout so that the
> conditionally stuffed component is the middle one in the chain.  Is this
> DDR2, or DDR3?
>
> Steve
>
> maheshwari palanisamy wrote:
>> hi team,
>> I am currently designing a processor module. In this case, I have a
>> processor
>> which can support 16bit DDR and supports 2 chip selects.
>>
>> To get the benifit of price, I am planning to use both the chipselects.
>> But
>> stuff only one DDR for lower memory requirements and will not stuff the
>> second DDR. Both DDR will be stuffed only for highest memory
>> configuration.
>>
>> In the case of only one DDR been stuffes, will the stubs in the DDR
>> address &
>> data create issue because of reflections? And Is this recommended to
>> stuff
>> one alone?
>>
>> Thanks in advance.
>> Maheshwari
>>
>
>
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