[SI-LIST] Re: DDR Test Cases - Address Line Short test

  • From: "T, Raghavendra (EE Bangalore)" <raghavendra.t@xxxxxx>
  • To: 'steve weir' <weirsi@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 23 Jun 2011 07:15:48 +0000

Dear Steve,
This particular piece of code is in standard u-boot.

(attached)

And to cross check the test code - After write operation, we manually the 
changed few memory locations (Without shorts).

After this we executed the READ operation? 

Our code reads executed till the changed memory location and stopped at the 
location of changed location.

I hope this test confirms test suite is fine?

Any comments or suggestion please do let me know,


Regards,
Raghavendra



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of steve weir
Sent: Thursday, June 23, 2011 12:31 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Test Cases - Address Line Short test

A properly coded address line or data line fault test always finds 
address and/or data lines that are shorted by etch to other address or 
data lines or either power rail.  If the test does not detect a short it 
is because the test design is deficient or the code fails to implement 
the design.

Steve.

On 6/22/2011 11:48 PM, T, Raghavendra (EE Bangalore) wrote:
> Dear All,
>
> We all know there are few specific test suites for testing the DDR_X SDRAM 
> interface (X = 1,2,3).
>
> In the boot-loader I see a test case mentioned as "address line test" I have 
> attached the file.
>
> The test should check for Shorts on Address line, if so any.
>   -  - - - - - - - - - -
> * This function performs a test to verify that all the address lines hooked 
> up to the RAM work properly.  If there is an address line fault, it usually 
> shows up as two different locations in the address map (related by the faulty 
> address line) mapping to one physical
>   Memory storage location.  The artifact that shows up is writing to the 
> first location "changes" the second location.
>
> - -  -- - - - - - - -  -
>
> Just to test this - I manually shorted few address lines (I mean - A0 shorted 
> with A1, A2, and A3 etc)
> But when I run the test - its not finding the error?  The memory seems to be 
> same as usual.
>
> I mean - in-spite of short - the memory works as if there is no short? i 
> manually checked (in board powered off state) the A0 is shorted with A1,A2, 
> A3 using Multimeter?
>
>
>
> First to cross check:
>
> We made sure the code is working fine:
>
> First we wrote to complete memory (a known pattern without short) - and 
> before we read, we modified the memory location values, the When code is made 
> to read back, we could see the it halts exactly at the changed location.
> This confirms that Firmware is fine.
>
> But when we manually short the Address Lines - after/before write operation - 
> it's not detecting?
>
> My few queries are:
>
>
>   1.  Can't we short the Address lines across? If not, then why such a test 
> case is there in u-boot?
>   2.  These address lines are pulled to VTT, I also cross checked in few 
> board where we do-not have VTT?
>   3.  Is it related to current /voltage driven logic?
>   4.  If I use the Oscilloscope - if I short few lines, how the waveform look 
> like, what could be the voltage? Is their any relationship?
>
>
>
> Regards
> Raghavendra
>
>
>
>
>
>
>
>
>
>
>
>
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Steve Weir
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