[SI-LIST] Re: DDR Interface Topology
- From: steve weir <weirsi@xxxxxxxxxx>
- To: arjun.bingipur@xxxxxxxxxx,<si-list@xxxxxxxxxxxxx>
- Date: Sat, 04 Nov 2006 00:11:34 -0800
Arjun, how you address this design depends a lot on the particular
FPGA you have selected and the width of the address and data
busses. The FPGA will determine how you approach both timing match
and cross talk with respect to floor planning the FPGA and physically
planning the PCB. I strongly suggest that you obtain assistance from
your FPGA vendor to insure that you have selected an appropriate
device and employ it within its capabilities. You have a number of
issues to manage that may each become quite challenging depending on
your data rate and PCB constraints.
Steve.
At 11:53 PM 11/3/2006, Bingipur, Arjun wrote:
>Hi,
>
>We are designing a FPGA based system with four DDRs interfacing
>independently with the FPGA. Here, all the address, data and control
>signals are point-to-point. I can see that Balanced T Routing topology
>is preferred where in the data and strobe signals are point-to-point and
>address/control is point-to-four-point. I'm curious to know if there is
>preferred routing topology and length matching schemes where in all the
>DDRs interface independently with the FPGA with its own address, data
>and control signals. Or, is it just that I'll have to make sure the
>lengths are matched for each data group and across the entire channel.
>
>Regards,
>Arjun Bingipur
>
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