[SI-LIST] Re: DDR Eye diagrams
- From: ji-wei_du@xxxxxxxxxxx
- To: david.novak@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 28 Jul 2004 12:18:19 +0800
Hi David :
You are right . The challenge is that the traditional eye-diagram =
analysis method is not good for DDR . Let me introduce a new way to do =
that .
I am not sure what you are working with , DDR chipset , DIMM , =
motherboard .... ? Anyway, let me try to give some comments.
=20
1. If you are measuring timing only , say , tAC, tDQSCK , ....=20
a) Acquiring CLK , DQS , DQ first , define the reference edge for =
the eye-diagram , say , both rising edge for clock .
b) Folding all the rising edges to the reference point (scope's =
trigger point) then get a real time eye-diagram of DQ .
With this method , there is no trigger jitter , no dead time =
with the scope .=20
You can identify the read or write by the timing easily .=20
c) A mask can be used to find the worst casae timing for either =
write or read cycles . And you can unfolding the mask to the failure =
bits so that you can measure the exact timing or signal integrity =
related to it .
( Please note that you should not set the trigger condition on one =
channel and get eye-diagram on another channel with traditional method =
, that just do not work for DDR)
=20
With the above method , you can measure many timing paramters =
simultaneously and get the worst case quickly .
2. If you are measuring signal integrity ,including crosstalk ,SSN ... =
, you may want to isolate write cycles eye-diagram or read cycles =
diagram.
a) I guess you are using EDA simulation software also , it's very =
easy for you to know that the amplitude of DQ read signals at golden =
finger side (for a DIMM ) is much lower than that at the chipset pins . =
So , test the DQ , DQS , CLK at near gold finger side please . =20
b) Removing the lower amplitude information from the DQ signals , =
then only write cycles are left and then you can get a real time =
eye-diagram based the method using in 1 . For DIMM side , only write =
is concerned . You get it .=20
c) You can define a mask for the eye-diagram , and do mask =
unfolding when there is any failure .=20
3. Alternative solution :
Read pre-amble is ~ 1 clock cycle , write preamble is not fixed , =
it can vary from 0.25 cycle to ~ 1 clock cycles , depends on the =
vendors you are working with .=20
Sometimes, trigger on preamble can work if write and read =
preamble are different . To minimize the trigger jitter caused by the =
scopes , you need a software to get an accurate eye-diagram display . =
(preamble is a negative pulse)
I have hundreds of screenshot of DDR eye-diagram measurements .
Certainly , this solution is using a software based on an =
oscilloscope .=20
I am not sure whether it can be of help . It will not help if the =
scopes you are using is different with mine .
Regards
Jiwei Du
Product Line Manager=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx =
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Novak David
Sent: 2004=E5=B9=B47=E6=9C=8828=E6=97=A5 11:19
To: si-list
Subject: [SI-LIST] DDR Eye diagrams
For measuring DDR eye diagrams, the best location to measure reads is =
at =3D
the memory controller and the best place to measure writes is at the =
=3D
DDR. For example, measuring reads at the DDR will show more reflections =
=3D
than actually seen by the memory controller (I should mention that I =
=3D
have only series termination).
This sounds simple, but I cannot think of a way to make the scope =3D
differentiate between reads and writes. You might suggest that I create =
=3D
a memory test which only does reads or only does writes. However, my =
=3D
worst case signals are when the entire system is running.
Can anyone tell me how to make the scope trigger only on reads or only =
=3D
on writes?
Thanks,
David
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=20
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