[SI-LIST] Re: DDR Clock & Length Matching
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: <kenny_frohlich@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 10 Jan 2007 21:06:05 -0800
Hi Kenny,
First rule, as always, is to check the controller design guide or app
notes to see if they
support external clock buffers. If you do use one, I assume it would be
a zero delay buffer,
otherwise you will distort the controller's timing assumptions. Perhaps
you could compensate
by shifting the length matching window, however, consider that a normal
DDR2 interface using UDIMM or SO-DIMM modules typically drives 4 CLKs
per controller CLK pin.
They use a balanced Tree topology with a termination on left and right
side. I don't know
anything about PowerPC but I have to assume the CLK buffer expects to
drive at least that
many SDRAM devices. If so, you can avoid the hassle of the external
buffer. Most controllers
have design guidelines based on driving a standard module, in which case
you can reverse=20
engineer the guidelines for a memory down implementation, using a module
spec. Or perhaps
they include memory down routing guidelines.=20
To answer your question, if you did brute force it with an external
buffer you would match to
the total path delay, or length #2, but you would also have to include
the prop delay of the
buffer and/or the timing skew of a PLL based buffer.=20
My advice would be to research the direct 4 load clock topology, as you
can find in a SO-DIMM
module spec. At least that would be my first inclination. =20
Brian P. Moran
Intel Corporation=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kenny Frohlich
Sent: Wednesday, January 10, 2007 7:38 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR Clock & Length Matching
Hi All,
I'm working on a design based on PowerPC PPC440EPx with DDR2. The
DDR2 bus consists of four onboard SDRAMs, but the PPC440EPx has only one
DDR clock so I have to use a clock buffer to provide four DDR clocks to
four SDRAMs (PPC440EPx --> Clock Buffer --> SDRAMs). For memory bus, I
have to match the length of Addr/Control lines to the clock. My
question is what is the length of the clock that I need to match?
=20
1) The length from the clock buffer to SDRAM
or
2) The total length: from PPC440EPx to clock buffer + from clock
buffer to SDRAM.
=20
Thanks,
Kenny
=20
=20
=20
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=20
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