I'd refer everyone to this gEEk SpEEk presentation done by Gus Blando a few
weeks ago. Bottom line is that it depends. On short links, capacitor
placement and antipad compensation can make a noticeable difference. In
other cases, it does not. YMMV.
https://blog.samtec.com/wp-content/uploads/2020/06/06_04_2020_geek_speek_DC_blocking_caps.pdf
https://vimeo.com/426327915
On Mon, Aug 31, 2020 at 1:22 PM Westerhoff, Todd <Todd_Westerhoff@xxxxxxxxxx>
wrote:
Totally agree - it's important to look at optimizations like plane cutouts
from how they affect the link's operating margin, not just as exercises
unto themselves. If the difference in operating in margin is minimal - who
cares? More importantly, why would I give up part of a plane layer if there
wasn't a significant benefit from the system perspective? I also agree that
COM is a particularly useful tool for assessing these kinds of tradeoffs -
it's fast enough to run in real time when you're evaluating design
alternatives.
As it happens, Min Maung and I are presenting a webinar next week from
tomorrow on exactly this topic - we even evaluate a blocking cap with and
without the plane cutouts to see the effect on the channel's COM score.
Fair warning: this webinar is meant for someone who's relatively new to
SerDes design, so some of the discussion on EM behavior are bit basic
(although you might find the analogies useful for explaining things to
coworkers). However, the second part of this webinar shows what we've
discussed here: using COM analysis to assess the impact of different
physical effects on channel margin and evaluating design tradeoffs like
blocking cap plane cutouts.
Should you be interested, you can register for " Automating Post-Route
Verification for Multi-Gigabit Channels" here:
https://www.mentor.com/pcb/series/shift-left-webinar-series. You can also
view the recording of the previous webinar "Designing SerDes Channels for
Protocol Compliance" which covers the same topics from a pre-route
standpoint.
Hope that helps,
Todd.
Todd Westerhoff
High-Speed Design Product Marketing | Electronic Board Systems
300 Nickerson Rd, Marlboro, MA 01752
todd_westerhoff@xxxxxxxxxx | office: 508-303-5821 | cell: 978-846-0203
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scotty Neally
Sent: Friday, August 28, 2020 4:21 PM
To: olaney@xxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; silr@xxxxxxxxxxx;
shashankdatta1218@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Cutout and Power reference for AC coupling Capacitor
Just my 2cents, with most engineering you have to decide where to focus
your efforts. I personally wouldn't spend 80% of my time trying to fix a
system impairment of 1-5% consequence (made up numbers). I agree that
depending on the context, optimizing the DC-blocking capacitor might not be
worth it, but knowing 'when' is important.
Some other factors:
-Location in the channel. Placement near connectors "smears" the impedance
discontinuity at slow edge rates -Equalization. If you can correct for
reflections with DFE or the channel ILD is low how much do you really care?
This becomes an ROI judgement based on how bad the impairments are.
-Stackup. Sometimes it's extremely difficult to optimize a blocking cap
due to GND/SIG plane ordering, density/proximity to other components, long
via, transitions, etc.
If you wanted to study this further you'd really need to look at DC
blocking cap effects at the system level with something like COM. However I
don't think you can conclude that there's no SI effect just because it's in
the noise of the channel...it's like saying diff via optimization or pad
stack has no consequence on SERDES design.
-Scotty
On Fri, Aug 28, 2020 at 12:30 PM Orin Laney <olaney@xxxxxxxxx> wrote:
So Scott and Scotty's paper is of no consequence? What edge rate didcraft"?
you use? And who is this mysterious person "who no longer practices our
...
-----Original Message-----
From: leeritchey@xxxxxxxxxxxxx <leeritchey@xxxxxxxxxxxxx>
Sent: Friday, August 28, 2020 10:48 AM
To: silr@xxxxxxxxxxx; olaney@xxxxxxxxx; shashankdatta1218@xxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Cutout and Power reference for AC coupling
Capacitor
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