[SI-LIST] Re: Current mode current stealing simulation by IBIS file

  • From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 25 Feb 2004 09:21:14 -0800

Sogo,

I am not sure what "current mode current stealing" is, but
to respond to the rest of your question I would like to say
that there must be another reason that makes your IBIS
simulation different from SPICE or measured.

In terms of the IV curve of a device or its simulation there
is really no such thing as current or voltage mode.  The shape
of the IV curve determines it all.  If your IV curve is a
horizontal line, you have an ideal current source.  If your
IV curve is a vertical line, you have an ideal voltage source.
If your IV curve is a diagonal line of some slope, you have
a linear resistor, and finally if you have a curved IV curve
you have a (non linear) diode, transistor or some sort of a
device.  There are no ifs and buts about this.  You tool may
select current as a known and voltage as the unknown, or vice
versa, but the model is still the same IV curve.

If there are discrepancies between your SPICE and IBIS models
that means that either the IV curves are not the same, or there
are perhaps other elements (or behaviors) in the SPICE model
which are not described by the IV and Vt curves of your IBIS
model.  If there are features in the buffer which are fancy
(dynamic) effects that IBIS 3.2 cannot describe with its
relatively simple IV and Vt curve approach, you may need
to resort to *-AMS as your modeling language as Lynne
suggested.  But this would not fall into the definition
of "current mode" vs. "voltage mode".

I hope this helps,

Arpad Muranyi
Intel Corporation
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Sogo Hsu
Sent: Wednesday, February 25, 2004 12:11 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Current mode current stealing simulation by IBIS file


Hi, Gurus,

A question regarding current mode current stealing circuit=20
simulation confused me for a long time. The simulation results=20
totally different from the measured as well. To understand the cause=20
of discrepancy, I tried to set up two kinds of circuit, one is=20
voltage mode and the other one is current mode. In general, IBIS=20
file describe the v/t curves of I/O cell with test feature. We can=20
easily generate the same v/t curve for these two. However, the Spice=20
simulation indicated the results are totally different if the whole=20
link is under considered. The behavior of current mode spice model=20
is similar with the measured. In my opinion, this phenomenon can be=20
analog to TE and TM mode. Therefore, the refection condition is=20
definitely different even they have owned same v/t curve in IBIS=20
file. My question is, how we overcome this issue if we only use IBIS=20
file for simulation. In general, we can only get IBIS files from=20
vendors.=20
Can any expert on this topic share the experience to me? Thank you=20
in advance.

Best regards,

Sogo Hsu, Ph. D.
Simulation center/PCEG/Foxconn Electronic

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