[SI-LIST] Re: Core or prepreg between signal and plane layers

  • From: "Rose, Michael" <mrose@xxxxxxxxxxxxxxxxx>
  • To: "johan.lans@xxxxxxxxxxxxxxx" <johan.lans@xxxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 19 Oct 2012 17:04:10 +0000

Johan, This is the common foil arrangement with B-stage on top and bottom. 
Holding impedance tolerance is affected when referencing to plane separated by 
prepreg. Lee Ritchey has been beating the drum on this for ages. The fab can 
control etchback to center the error within the likely variation in prepreg 
thickness determined when qual'ing the material. In my experience, holding 
+/-10 is not generally not a problem - maybe +/- 5% is another story?

Mike

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Johan Lans
Sent: Friday, October 19, 2012 12:53 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Core or prepreg between signal and plane layers

Hi
 I'm working on a 16 layer board for video processing. There will be 100 Ohm 
differential pairs for 3Gbit digital video signals. Stackup is signal on top 
layer, 2nd layer power, 3rd gnd, 4th signal, 5th signal, 6th power, 7th gnd and 
so on.
The manufacturer of the board wants to put prepreg between lyr 1 and 2, 3 and 4 
etc and core between 2 and 3, 4 and 5 etc. A collegue of mine claims that this 
stackup will give a less uniform impedance of the diff pairs, since the 
distance from signal to plane layer will vary more due to the initial softness 
of the prepreg. The manufacturer will produce a board with core between signal 
and plane for a higher price, since layers registration will be more difficult. 
Does anyone know how much this effect matters, and if it's worth the money to 
get the more difficult to produce board?
/Johan


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