[SI-LIST] Re: Controlled Impedance Calculation for a 8-Layer Stack-up
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <agrawal.gaurav@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 14 Feb 2003 23:54:33 -0800
It looks like you have a reference plane next to the surface layers.
Isn't it Micro-strip?
What am I missing?
(Well, the reference is two layers away but it is still there).
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Gaurav Agrawal
Sent: Friday, February 14, 2003 9:48 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Controlled Impedance Calculation for a 8-Layer
Stack-up
Hi All,
We are using a 8-layer stack for a telecom board design. The
configuration we will be using is as follows:
Top Layer
Layer 2 (Signal)
Layer 3 (Ground)
Layer 4 (Signal)
Layer 5 (Signal)
Layer 6 (Power)
Layer 7 (Signal)
Bottom Layer
Regarding the calculation of the controlled impedance for all the
layers, we have used a tool ULTRACAD. It is able to give us the results
for all the configurations except for the surface layers, the reason
being that their is no reference plane next to these layers.
I would like to know if anyone here has an idea regarding a tool which
provides such configurations. Or else, if someone can provide us with a
set of formulae to work upon.
Best Regards
Gaurav Agrawal.
Project Engineer,
Wipro Technologies,
SP Road, Begumpet,
Hyderabad - India.
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