[SI-LIST] Re: CDR with SJ > 1UI
- From: "T.K. Jeon" <tkjeon@xxxxxxxxxxx>
- To: "ah.vinod@xxxxxxxxx" <ah.vinod@xxxxxxxxx>, SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Fri, 18 Jan 2013 18:55:49 -0800
Hi Vinod,
It doesn't matter if the data eye is closed due to just phase variations. The
data signal still has transitions even if SJ is more than 1UI and CDR can take
those transitions and recover the clock. If the eye closure was due to ISI or
other amplitude noise, that's a different story.
The tolerable amplitude of SJ is like this: Let's say the loop feedback gain of
your CDR is unity and the loop transmission is G(s), then the transfer function
of the CDR is Phi_clk/Phi_data = G(s)/(1+G(s)).
Thus, the transfer function of your overall Rx block will be
(Phi_clk-Phi_data)/Phi_data = 1- (Phi_clk/Phi_data) = 1/(1+G(s)).
Based on the above equation, Phi_data(max) = (1+G(s))(Phi_data-Phi_clk) =
(1+G(s))*2*pi*(1-T_delta) = (1+G(s))*(1-T_delta) in UI unit, where T_delta is
the untracked jitter from CDR.
Keep in mind here that the G(s) includes gains from a phase detector and an
integrator with LPF, hence the amplitude of Phi_data(max) can be more than 1UI
at very low frequencies.
Best Regards,
TK
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of vinod ah
Sent: Thursday, January 17, 2013 9:39 PM
To: SI-LIST
Subject: [SI-LIST] CDR with SJ > 1UI
Hi,
I have a basic query on serial data analysis. I am working on 5Gbps serial
link where Rx jitter tolerance test states that at 100KHz SJ with 200% UI
amplitude, we should meet BER of 1 in 10^-12.
But the part i am not able to understand is with 2UI Jitter, how will the
eye be opened as 2UI jitter means that the edge of data is shifted by an
amount greater than 1UI which means the eye is closed !!. I am not sure how
CDR circuits can recover clock with this much jitter as it might easily
fall out of the loop bandwidth.
Can serial data experts help me out in understanding the concept of eye
opening with jitter > 1UI and how CDR circuits work with such high jitter?
I went several articles on google, but for some reason was not able to find
a convincing answer.
Regards
Vinod A H
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