[SI-LIST] Re: Buried capacitance layer; ? Area to use? Use with discrete caps?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Ken Cantrell <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- Date: Wed, 04 Jun 2008 07:30:06 -0700
Ken, no the characteristic impedance is a function of thickness and eR.
Below modal resonances, using the same resin / glass proportions a 40mil
cavity has 10X the impedance of the same shape 4mil cavity. At the
modal resonances the Q of the 40 mil cavity is much higher than that of
the 4mil cavity making the impedance peaks much worse than 10X. Istvan
notes that once the cavity gets down to about 0.3mils that the modal
peaks are essentially fully suppressed.
The minima are a result of wave modes that depend on the size, shape and
eR of the cavity ( until you get really thin and then skin resistance
and tangent loss shift the frequency downward further ), and the probe
point location.
Best Regards,
Steve.
Ken Cantrell wrote:
> Steve,
> Just a clarification if you would. Is plane self-imepedance down shifting
> due to plane thickness a property of very thin laminates only? Reference
> Istvan Novak's book,"Frequency-Domain Characterization of Power Distribution
> Networks", Figure 4.24, page 93. At 250 microns (~10 mils), and at 25
> microns (~ 1 mil), the impedance minima appear to be at the same frequency.
> Increasing the area downshifts the frequency of the dominant mode impedance,
> and increasing the permittivity does the same thing. But for applications
> where the plane spacing is 1 mil or greater, would it seem reasonable to
> assume that the plane impedance is not downshifted as plane separation is
> decreased?
> Thanks,
> Ken
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
> Sent: Tuesday, June 03, 2008 7:01 PM
> To: tom_cip_11551
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Buried capacitance layer; ? Area to use? Use with
> discrete caps?
>
>
> Tom, it is not so much how much capacitance that the IC will see, but
> what is the impedance versus frequency. The plane cavity behaves as a
> two dimensional transmission structure. At low frequencies the
> inductance of the structure dominates and this appears in series with
> the mounted inductance of the bypass caps. Here, thinner is better as
> it gets you lower inductance interconnect allowing you to get away with
> fewer capacitors for the same total inductance.
>
> Assuming a fairly even distribution of capacitors, the cavity takes over
> at a frequency determined by the type of capacitors, how they are
> mounted, their density, the location of the cavity in the stack-up, as
> well as the thickness and eR of the dielectric. The thinner you go, the
> lower this cross-over frequency tends to be. Once you hit that
> crossover frequency your IC will see less and less of the bypass network
> and more and more the cavity only. If the cavity is a perfectly damped
> structure, then it will see that impedance without impedance peaks or
> valleys. If the cavity is not well damped, then the impedance will have
> peaks and valleys. One of the charms of thin dielectrics is that they
> are inherently lower Q, and so the relative magnitude of the peaks and
> valleys is lower on top of a lower characteristic impedance to boot.
> For example 1 mil material typically has 1/8th to 1/10th the peak
> impedance of 4 mil material in otherwise identical circumstances.
>
> There isn't a buried capacitance material in the world that has a high
> enough eR to eliminate discrete bypass caps. People can screw-up using
> thin dielectric at least two different ways:
>
> 1. They create a nasty resonance between the bypass caps and the power
> cavity inside the signaling / sensitivity bandwidth of the load. This
> is easier to do with thin dielectrics, because the cross-over frequency
> comes down versus thicker, lower performance dielectrics. The remedies
> for this are straightforward.
>
> 2. They fail to pay attention to energy near the PCB edges. Thin
> dielectrics have lower characteristic impedances, meaning they store
> more energy than thick dielectrics. When that energy reaches the edge
> of the PCB a certain amount couples to the outside world. How you do
> your stack-up, whether you make a good via fence, and/or do something to
> dissipate that energy all impact how much couples out as EMI.
>
> So, to get down to your real question: How to design the bypass network
> with thin dielectric?
>
> 1. Establish a target impedance from what you can find out about your loads.
> 2. Recognize what the impact of the Z axis from wherever you would like
> to put the cavity in your PCB stackup to the IC die is.
> 3. Design the combined bypass / interconnect to minimize the impact of
> resonances. This means managing the cross-over points:
> a. Between bypass caps of different values
> b. Bypass caps and any IC die / in package capacitance
> c. Bypass caps and the cavity you design
>
> Steve.
> tom_cip_11551 wrote:
>
>> Hi Si-List PCB design experts.
>>
>> If I had a large buried capacitance layer, a vcc and ground, and stuck
>> a single part in the center of it requiring decoupling, how much
>> capacitance would the vcc pin of the part actually "see"? Is this a
>> distributed capacitance? I know that they say to use a rule of thumb
>> like 500 pF/in2. But for each square inch of buried capacitance that I
>> use does the sum add linearly?
>>
>> In my case, I am considering using a buried capacitanc layer in a pcb
>> where the switching is done at 4Gb/s. I have several circuits that are
>> identical but not running on the same supply, so the area of buried
>> capacitance will not be all that large.
>>
>> My original concept is to use a small section of buried plane for high
>> speed switching and have some larger decoupling caps (.01 uF 402)
>> connected through vias to make up for what the plane can not handle at
>> lower frequencies. Now if I use, say, a square inch of buried plane per
>> device, that would amound to something like 500 pf of plane capacitance
>> and .01 uF of discrete. Generally speaking, is this too small of a
>> buried capacitance to use?
>>
>> Finally, I have read that using discrete caps and buried capacitance
>> can give more problems with respect to EMI than using each alone. Is
>> this true?
>>
>> Thank you to all who respond.
>>
>> Tom
>>
>>
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>>
>>
>
>
> --
> Steve Weir
> Teraspeed Consulting Group LLC
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(866) 675-4630 Business
(707) 780-1951 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax
http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
Teraspeed Consulting Group LLC
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Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC
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