[SI-LIST] Re: BGA Soldering
- From: sunil bharadwaz <sunil_bharadwaz@xxxxxxxxx>
- To: 'ClarkAlias1' <cjclark@xxxxxxxxxxxxxxx>, 'SI LIST' <si-list@xxxxxxxxxxxxx>, Aubrey Sparkman <asparkman@xxxxxxxxxxxxx>
- Date: Fri, 4 Dec 2009 10:39:33 -0800 (PST)
Hi Aubrey Sparkman ,
Thanks for the Reply !!
I really agree that co-planarity of the board & package could be a issue.
This is true because some chip which does not work on one board works
on another.
However , is there a way to establish the co-planarity of the boards.
We do get the boards checked for the Warpage.However , that
does not seem to be sufficient.
Regards
Sunil.B
--- On Thu, 12/3/09, Aubrey Sparkman <asparkman@xxxxxxxxxxxxx> wrote:
From: Aubrey Sparkman <asparkman@xxxxxxxxxxxxx>
Subject: RE: [SI-LIST] Re: BGA Soldering
To: "'ClarkAlias1'" <cjclark@xxxxxxxxxxxxxxx>, "'sunil bharadwaz'"
<sunil_bharadwaz@xxxxxxxxx>, "'SI LIST'" <si-list@xxxxxxxxxxxxx>
Date: Thursday, December 3, 2009, 11:08 PM
Sunil,
You might try a sonic scan. Acoustic techniques have been known to pick up
cracks that hide from Xrays.
You may also check co-planarity of the package/board assembly and the
package co-planarity after the LGA has been removed. I have seen this
phenomena (fail until the LGA is removed and pass after a part that meets
co-planarity specs is put back on) before -- the failing parts all failed
co-planarity tests but passed all the standard electrical continuity tests.
As CJ points out, the biggest challenge is testing the power and ground
pins.
Aubrey Sparkman
Aubrey.K.Sparkman@xxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of ClarkAlias1
Sent: Thursday, December 03, 2009 10:49 AM
To: sunil bharadwaz; SI LIST
Subject: [SI-LIST] Re: BGA Soldering
Hello Sunil,
The limitations of X-Ray for opens testing is fairly well known. Shorts
Show up completely obvious, opens are a bit more subjective - the operator
(even 3D x-ray) has to decide if the shape is not what it should be. But,
Opens can still exist when the ball maintains a spherical shape but has A
high-resistive connection.
This one area that, my favorite standard, IEEE 1149.1 adds value in
electrically testing the connections for BGAs. I may be a bit biased as I
have chaired the standard since 1996. Some of you may know it as JTAG which
is the slang name.
Software tools exist to generate Test patterns automatically without the
need for 'domain expertise' in the system under test or the need to
write/embed functional software code. The other advantage is that because
the tests are algorithmic/mathematical, diagnostics are generated
automatically from diagnostic engines to pinpoint exactly the ball that is
failing. That goes a long way in improving the process when you know which
ball is giving you trouble.
There is an add-on to IEEE 1149.1 called 1149.6 which tests for stuck-ats on
AC coupled nets Which you typically would find on SERDES. This standard is
sometimes called ACJTAG but it is a bit of a misnomer as there is no
at-speed test - it's not AC parametric but AC coupled.
The 1149.6 support has to be designed in, and unfortunately some devices
like a Xilinx V5 Do not support 1149.6 correctly - so at-speed JTAG test is
all that is available for those Solder balls. SERDES BER through JTAG is
done, however there is currently no IEEE standard, There are commercial
products that let you execute and embed SERDES BER tests.
What's interesting is that there are assumptions that at 25 degrees Celsius
if a ball is good at X-ray it is good across all temps and all board flexing
despite the properties of the materials having different coefficients of
thermal expansion. Plug a board into a system, next To other boards and
there is heat, humidity differences. So during system builds Or in the
field new mysterious failures can occur. IEEE 1149.1/JTAG test can easily
be embedded today with a $10 IC which can run these interconnect tests (and
other at-speed tests like SERDES BER, DDR MemoryBIST, ASIC BIST etc) and
record/log the failures to further drill into failure analysis - and avoid
the no-trouble-found when the board gets back to depot repair.
Some areas that need improvement: The standard doesn't enable this test for
Power and Ground Pins directly. There are many indirect ways, especially
with FPGAs to test that all the power/gnd pins are connected but it's not
built into the IEEE standard itself. I currently have a working group that
is looking at what can be done in this area. There are some Deficiencies on
self-monitoring low voltage pins, which we are looking at as well.
I hope this info helps. Maybe a little off-topic for SI but related.
Regards,
CJ
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Lower your electronic product cost with Intellitech and Standards
CJ Clark PH:603-868-7116 x115
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of sunil bharadwaz
Sent: Thursday, December 03, 2009 8:13 AM
To: SI LIST
Subject: [SI-LIST] BGA Soldering
Hi Experts ,
While trying to solder some LGA's , we are seeing some strange issues.The
XRAYS & the Die penetration test reveal the Soldering is Okay.However , the
performance of the board reveals that there is a soldering issue.When we
replace the LGA with another chip , the board works fine.Of course even the
original LGA works fine when re soldered on some other board.
I guess the XRAY & the Die penetration test cannot be 100 % conclusive
regarding the Soldering quality.
Is there any way to establish the soldering quality authentically.I mean to
say are there any better tests ?
Thanks in Advance.
Regards
Sunil Bharadwaz
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