[SI-LIST] Announcement of On-line Course Event: Mastering the DDR3 Memory Architecture: Layout, Simulation and Analysis
- From: "Hany Fahmy" <hanymhfahmy@xxxxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 26 Sep 2013 19:03:57 +0200
Content-Type: multipart/alternative;
boundary="----=_NextPart_002_0048_01CEBAEB.269F5460"
------=_NextPart_002_0048_01CEBAEB.269F5460
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: 7bit
Hi All,
I am sending an announcement of an On-Line Course event "Mastering the DDR3
Memory Architecture: Layout, Simulation and Analysis".
Pls. access the following link for more details:
http://www.fedevel.com/academy/online-course-understanding-high-speed-ddr3-l
ayout-simulation-and-analysis/
Pls. fill in the survey so that we can fulfill your needs for the technical
content of DDR3 memory channel architect.
About the Class:
Memory Channel design is very challenging especially with such wide
interface (every channel has ~ 124 signals to route) single-ended signals
reaching such high data rates as DDR4 running at 4.266GB/s per copper lane
at low-voltage of 1.05V while GDDR5 running at 7GHz clock and processes
28GB/s with 32-bits I/O. Special consideration is required when routing
these mm-wave signals as the spectral content easily reaches 30GHz. In this
course, we will start from "paper and pencil Analysis", then move to
"Feasibility Analysis" using appropriate simulation tools, then study the
high sensitivity parameters of the channel to develop crisp
design-guidelines that are controlled by cost, power and performance.
Today's industry drive a strict requirement on cost/power/performance while
striving for speed-of-light products that reaches the market before
competition. Also, with such mm-wave signals propagating through the
channel, we need to have accurate prediction of signal-quality,
power-deliver noise and radiated-emission all at once. The course will
outline the design trade-off between meeting the required eye-mask while
controlling the simultaneous-switching noise on the power-rails along with
limiting EMC to pass the required certification requirements.
What will you learn?
You will learn how to architect a DDR3 memory channel: Simulate, Improve,
Analyze and Validate a DDR3 interface.
How will you learn?
Best Known Process (BKP) of layout and simulation: we will start with
pre-layout simulations to develop the design-guidelines, then start routing
the most critical nets of the memory channel, fine-tune the simulations to
meet the required performance, then routing all nets and validate the
performance through post-layout simulations. The process will assure to meet
the performance target of your PCB from the first revision. We will walk
through the BKP using real example of an SBC that suffers failure then show
you the pathway to meet the performance target in shortest time to market.
What you will learn?
This course is all about DDR3 design:
* Developing Design-Guidelines - Perform pre-layout simulations to
find out the optimum routing of the each signal group. We will take as an
example: Data and Clock-nets routing.
* Optimization of the routing - Find optimum width/spacing of each
section of the routing: break-out/fan-out, main-section then fan-in or
break-in sections, which layer to route the data-signals and what
referencing scheme should they use.
* Interaction between Routing & Simulations - Learn to build an
interactive process between pre-layout simulations and Routing the signals,
fine-tuning between the constraints of layout vs. simulations to achieve a
reasonable performance constrained by the physical routing.
* Routing the worst-case byte lanes & Clocks- You will start routing
the worst-case byte lanes (8-DQ signals + DQS/DQS# + DM) and clock signals.
The pre-layout simulations will show the worst-case byte lanes, e.g., bytes
that are 4.5" inch long die-2-die as an example.
* Post-layout simulations - You will perform post-layout simulations
to extract the S-parameter model of the worst-case byte lanes, then do
'what-if' analysis and further fine-tune the routing to achieve the
performance vs. cost vs. power target.
* Validate the performance - You will continue routing all byte lanes
and repeat the post-layout simulations to validate the performance target of
the design.
* Route Address/Command signals - You will then move to routing the
next group of Address/Command and control signals then repeat the
interactive process above.
Have a wonderful day all,
Hany Fahmy
CEO & Chief Consultant Officer
Intelligent Solutions BVBA
hanymhfahmy@xxxxxxxxxxxxxxxxxxx <mailto:hanymhfahmy@xxxxxxxxxxxxxxxxxxx>
http://www.intelligentsolutionsbvba.com/
http://www.linkedin.com/pub/hany-fahmy/66/852/b11
Phone: +32471650724
This email and any files transmitted with it are confidential and intended
solely for the use of the individual or entity to whom they are addressed.
If you have received this email in error please notify the system manager.
Please note that any views or opinions presented in this email are solely
those of the author and do not necessarily represent those of the company.
Finally, the recipient should check this email and any attachments for the
presence of viruses. The company accepts no liability for any damage caused
by any virus transmitted by this email.
------=_NextPart_002_0048_01CEBAEB.269F5460
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<html xmlns:v=3D"urn:schemas-microsoft-com:vml" =
xmlns:o=3D"urn:schemas-microsoft-com:office:office" =
xmlns:w=3D"urn:schemas-microsoft-com:office:word" =
xmlns:m=3D"http://schemas.microsoft.com/office/2004/12/omml"; =
xmlns=3D"http://www.w3.org/TR/REC-html40";><head><META =
HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii"><meta name=3DGenerator content=3D"Microsoft Word 15 =
(filtered medium)"><!--[if !mso]><style>v\:* =
{behavior:url(#default#VML);}
o\:* {behavior:url(#default#VML);}
w\:* {behavior:url(#default#VML);}
.shape {behavior:url(#default#VML);}
</style><![endif]--><style><!--
/* Font Definitions */
@font-face
{font-family:Wingdings;
panose-1:5 0 0 0 0 0 0 0 0 0;}
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
@font-face
{font-family:Verdana;
panose-1:2 11 6 4 3 5 4 4 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:11.0pt;
font-family:"Calibri","sans-serif";}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:#0563C1;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:#954F72;
text-decoration:underline;}
span.EmailStyle17
{mso-style-type:personal-compose;
font-family:"Calibri","sans-serif";
color:windowtext;}
.MsoChpDefault
{mso-style-type:export-only;
font-family:"Calibri","sans-serif";}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
/* List Definitions */
@list l0
{mso-list-id:1177187141;
mso-list-template-ids:23468000;}
@list l0:level1
{mso-level-number-format:bullet;
mso-level-text:\F0B7;
mso-level-tab-stop:.5in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Symbol;}
@list l0:level2
{mso-level-number-format:bullet;
mso-level-text:o;
mso-level-tab-stop:1.0in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:"Courier New";
mso-bidi-font-family:"Times New Roman";}
@list l0:level3
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:1.5in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
@list l0:level4
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:2.0in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
@list l0:level5
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:2.5in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
@list l0:level6
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:3.0in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
@list l0:level7
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:3.5in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
@list l0:level8
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:4.0in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
@list l0:level9
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:4.5in;
mso-level-number-position:left;
text-indent:-.25in;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
ol
{margin-bottom:0in;}
ul
{margin-bottom:0in;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext=3D"edit" spidmax=3D"1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext=3D"edit">
<o:idmap v:ext=3D"edit" data=3D"1" />
</o:shapelayout></xml><![endif]--></head><body lang=3DEN-US =
link=3D"#0563C1" vlink=3D"#954F72"><div class=3DWordSection1><p =
class=3DMsoNormal>Hi All, <o:p></o:p></p><p =
class=3DMsoNormal><o:p> </o:p></p><p class=3DMsoNormal>I am sending =
an announcement of an On-Line Course event “<u><span =
style=3D'font-size:12.0pt;font-family:"Arial","sans-serif";color:#333333'=
>Mastering the DDR3 Memory Architecture: Layout, Simulation and =
Analysis</span></u><span =
style=3D'font-size:12.0pt;font-family:"Arial","sans-serif";color:#333333'=
>”. </span><span =
style=3D'font-size:12.0pt'><o:p></o:p></span></p><p class=3DMsoNormal =
style=3D'mso-margin-top-alt:auto;margin-bottom:12.0pt'>Pls. access the =
following link for more details: <span =
style=3D'font-family:"Verdana","sans-serif";color:#333399'><a =
href=3D"http://www.fedevel.com/academy/online-course-understanding-high-s=
peed-ddr3-layout-simulation-and-analysis/" =
target=3D"_blank">http://www.fedevel.com/academy/online-course-understand=
ing-high-speed-ddr3-layout-simulation-and-analysis/</a></span><o:p></o:p>=
</p><p class=3DMsoNormal>Pls. fill in the survey so that we can fulfill =
your needs for the technical content of DDR3 memory channel architect. =
<o:p></o:p></p><p class=3DMsoNormal><o:p> </o:p></p><p =
class=3DMsoNormal =
style=3D'mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-line-heig=
ht-alt:15.75pt;background:white'><span =
style=3D'font-size:18.0pt;font-family:"Arial","sans-serif";color:#333333'=
>About the Class: <o:p></o:p></span></p><p class=3DMsoNormal =
style=3D'margin-bottom:15.0pt;line-height:15.75pt;background:white'><span=
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Memory =
Channel design is very challenging especially with such wide interface =
(every channel has ~ 124 signals to route) single-ended signals reaching =
such high data rates as DDR4 running at 4.266GB/s per copper lane at =
low-voltage of 1.05V while GDDR5 running at 7GHz clock and processes =
28GB/s with 32-bits I/O. Special consideration is required when routing =
these mm-wave signals as the spectral content easily reaches 30GHz. In =
this course, we will start from “paper and pencil Analysis”, =
then move to “Feasibility Analysis” using appropriate =
simulation tools, then study the high sensitivity parameters of the =
channel to develop crisp design-guidelines that are controlled by cost, =
power and performance. Today’s industry drive a strict requirement =
on cost/power/performance while striving for speed-of-light products =
that reaches the market before competition. Also, with such mm-wave =
signals propagating through the channel, we need to have accurate =
prediction of signal-quality, power-deliver noise and radiated-emission =
all at once. The course will outline the design trade-off between =
meeting the required eye-mask while controlling the =
simultaneous-switching noise on the power-rails along with limiting EMC =
to pass the required certification requirements.</span><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'><o:p></o:p></=
span></p><p class=3DMsoNormal =
style=3D'margin-bottom:15.0pt;line-height:15.75pt;background:white'><b><s=
pan =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif";color:#333333'=
>What will you learn?</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif";color:#333333'=
><br>You will learn how to architect a DDR3 memory channel: Simulate, =
Improve, Analyze and Validate a DDR3 interface.<o:p></o:p></span></p><p =
class=3DMsoNormal =
style=3D'margin-bottom:15.0pt;line-height:15.75pt;background:white'><b><s=
pan =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif";color:#333333'=
>How will you learn?</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif";color:#333333'=
><br>Best Known Process (BKP) of layout and simulation: we will start =
with pre-layout simulations to develop the design-guidelines, then start =
routing the most critical nets of the memory channel, fine-tune the =
simulations to meet the required performance, then routing all nets and =
validate the performance through post-layout simulations. The process =
will assure to meet the performance target of your PCB from the first =
revision. We will walk through the BKP using real example of an SBC that =
suffers failure then show you the pathway to meet the performance target =
in shortest time to market. <o:p></o:p></span></p><p class=3DMsoNormal =
style=3D'mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-line-heig=
ht-alt:15.75pt;background:white'><span =
style=3D'font-size:18.0pt;font-family:"Arial","sans-serif";color:#333333'=
>What you will learn?<o:p></o:p></span></p><p class=3DMsoNormal =
style=3D'line-height:15.75pt;background:white'><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif";color:#333333'=
>This course is all about DDR3 design:<o:p></o:p></span></p><ul =
type=3Ddisc><li class=3DMsoNormal =
style=3D'color:#333333;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto=
;line-height:15.75pt;mso-list:l0 level1 lfo1;background:white'><b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Developing =
Design-Guidelines</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'> –=
Perform pre-layout simulations to find out the optimum routing of the =
each signal group. We will take as an example: Data and Clock-nets =
routing.<o:p></o:p></span></li><li class=3DMsoNormal =
style=3D'color:#333333;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto=
;line-height:15.75pt;mso-list:l0 level1 lfo1;background:white'><b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Optimization =
of the routing</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'> –=
Find optimum width/spacing of each section of the routing: =
break-out/fan-out, main-section then fan-in or break-in sections, which =
layer to route the data-signals and what referencing scheme should they =
use.<o:p></o:p></span></li><li class=3DMsoNormal =
style=3D'color:#333333;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto=
;line-height:15.75pt;mso-list:l0 level1 lfo1;background:white'><b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Interaction =
between Routing & Simulations</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'> –=
Learn to build an interactive process between pre-layout simulations =
and Routing the signals, fine-tuning between the constraints of layout =
vs. simulations to achieve a reasonable performance constrained by the =
physical routing.<o:p></o:p></span></li><li class=3DMsoNormal =
style=3D'color:#333333;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto=
;line-height:15.75pt;mso-list:l0 level1 lfo1;background:white'><b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Routing the =
worst-case byte lanes</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'> <b>&=
; Clocks</b>– You will start routing the worst-case byte lanes =
(8-DQ signals + DQS/DQS# + DM) and clock signals. The pre-layout =
simulations will show the worst-case byte lanes, e.g., bytes that are =
4.5” inch long die-2-die as an example.<o:p></o:p></span></li><li =
class=3DMsoNormal =
style=3D'color:#333333;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto=
;line-height:15.75pt;mso-list:l0 level1 lfo1;background:white'><b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Post-layout =
simulations</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'> –=
You will perform post-layout simulations to extract the S-parameter =
model of the worst-case byte lanes, then do ‘what-if’ =
analysis and further fine-tune the routing to achieve the performance =
vs. cost vs. power target.<o:p></o:p></span></li><li class=3DMsoNormal =
style=3D'color:#333333;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto=
;line-height:15.75pt;mso-list:l0 level1 lfo1;background:white'><b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Validate the =
performance</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'> –=
You will continue routing all byte lanes and repeat the post-layout =
simulations to validate the performance target of the =
design.<o:p></o:p></span></li><li class=3DMsoNormal =
style=3D'color:#333333;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto=
;line-height:15.75pt;mso-list:l0 level1 lfo1;background:white'><b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'>Route =
Address/Command signals</span></b><span =
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif"'> –=
You will then move to routing the next group of Address/Command and =
control signals then repeat the interactive process above. =
<o:p></o:p></span></li></ul><p class=3DMsoNormal =
style=3D'margin-bottom:15.0pt;line-height:15.75pt;background:white'><span=
=
style=3D'font-size:10.0pt;font-family:"Arial","sans-serif";color:#333333'=
><o:p> </o:p></span></p><p class=3DMsoNormal>Have a wonderful day =
all, <o:p></o:p></p><p class=3DMsoNormal>Hany Fahmy <o:p></o:p></p><p =
class=3DMsoNormal>CEO & Chief Consultant Officer<o:p></o:p></p><p =
class=3DMsoNormal>Intelligent Solutions BVBA<o:p></o:p></p><p =
class=3DMsoNormal> &=
nbsp; <img border=3D0 width=3D107 height=3D103 id=3D"Picture_x0020_1" =
src=3D"cid:image001.png@01CEBAEB.25F42040" alt=3D"ISBVBA LOGO - =
small"> <o:p></o:p></p><p =
class=3DMsoNormal><a =
href=3D"mailto:hanymhfahmy@xxxxxxxxxxxxxxxxxxx";>hanymhfahmy@IntelligentSo=
lns.be</a><o:p></o:p></p><p class=3DMsoNormal><a =
href=3D"http://www.intelligentsolutionsbvba.com/";>http://www.intelligents=
olutionsbvba.com/</a><o:p></o:p></p><p class=3DMsoNormal><a =
href=3D"http://www.linkedin.com/pub/hany-fahmy/66/852/b11";>http://www.lin=
kedin.com/pub/hany-fahmy/66/852/b11</a><o:p></o:p></p><p =
class=3DMsoNormal>Phone: +32471650724<o:p></o:p></p><p =
class=3DMsoNormal><o:p> </o:p></p><p class=3DMsoNormal><i><span =
style=3D'font-size:9.0pt;font-family:"Courier =
New";color:black;background:white'>This email and any files transmitted =
with it are confidential and intended solely for the use of the =
individual or entity to whom they are addressed. If you have received =
this email in error please notify the system manager. Please note that =
any views or opinions presented in this email are solely those of the =
author and do not necessarily represent those of the company. Finally, =
the recipient should check this email and any attachments for the =
presence of viruses. The company accepts no liability for any damage =
caused by any virus transmitted by this email. </span></i><i><span =
style=3D'font-size:9.0pt'><o:p></o:p></span></i></p><p =
class=3DMsoNormal><o:p> </o:p></p></div></body></html>
------=_NextPart_002_0048_01CEBAEB.269F5460--
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
- » [SI-LIST] Announcement of On-line Course Event: Mastering the DDR3 Memory Architecture: Layout, Simulation and Analysis - Hany Fahmy
