[SI-LIST] Re: Analog/Digital vss connection for a PLL IC
- From: Faraydon Pakbaz <pakbazf@xxxxxxxxxx>
- To: mike_bihan@xxxxxxxxxxxx
- Date: Thu, 27 Apr 2006 10:09:32 -0400
Han;
You can tie analog vdd/vss and one pair of digital vdd/vss at board level
using ferrite bead and a capacitor(0.1 uf) . Recognize that you need to do
some simulation
with this filter and make sure it appropriately attenuates your low
frequency board noise.
A closed loop bandwidth plot of PLL can be very helpful to do the
comparison and judge
the performance of filter. That said, Opinions are wide as far as how you
implement the
analog vdd/vss and digital vdd/vss for PLL. I encourage you to
read a paper by Patrik Larsson with the title " Measurements and
Analysis of PLL Jitter Caused by Digital Switching Noise". It is
an IEEE paper. This paper describes various methods of handling
this with hardware data. Highly recommended reading. Hope this helps.
Regards;
Don Pakbaz
Silicon Solutions Engineering
IBM Systems & Technology Group
Bi Han
<mike_bihan@yahoo
.com.cn> To
Sent by: List` Si <si-list@xxxxxxxxxxxxx>
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Subject
[SI-LIST] Analog/Digital vss
04/27/2006 09:32 connection for a PLL IC
AM
Please respond to
mike_bihan@yahoo.
com.cn
Hi, folks:
Just wondering about an old question.
There is a PLL chip, it has one pair of analog vdd/vss and one pair of
digital vdd/vss. We will seperate vdds on chip and only connect them on the
board level.
My question is that shall we tie the analog vss with digital vss together
on the chip?
I've ever seen different types of answers on different forums, ppt,
papers. Anyone suggest a one-stop document for that kind of conundrum?
thanks,
Han
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