[SI-LIST] Re: Altera Unveils Innovations for 28-nm/28 Gbps FPGAs
- From: <Christopher.Jakubiec@xxxxxxxxxxxx>
- To: <mpli@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 8 Feb 2010 20:50:57 +0100
So, what is your question?
Chris
Infineon
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Mike Peng Li
Sent: Monday, February 08, 2010 2:34 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] FYI: Altera Unveils Innovations for 28-nm/28 Gbps FPGAs
Altera Unveils Innovations for 28-nm FPGAs
Press Release Source: Altera Corporation On Monday February 1, 2010, 12:00 pm
EST
SAN JOSE, Calif.--(BUSINESS WIRE)--Building on its history of technology
leadership, Altera Corporation (NASDAQ:ALTR - News) announced today new
innovations that will be incorporated into upcoming 28-nm FPGAs. Embedded
HardCopy(r) Blocks, a new method for partial reconfiguration and embedded
28-Gbps transceivers will dramatically improve the density and I/O performance
of next-generation Altera(r) FPGAs and further strengthen their competitive
position versus ASICs and ASSPs.
The rapid growth of bandwidth-intensive applications such as high-definition
(HD) video, cloud computing, online data storage and mobile video has created a
challenge for both infrastructure and end-user equipment developers. How can
they quickly increase system bandwidth while staying within strict power and
cost budgets? Altera has developed its latest innovations to solve these
challenges.
The new Embedded HardCopy Blocks are customizable hard intellectual property
(IP) blocks that leverage Altera's unique HardCopy ASIC capabilities. They are
used to harden standard or logic-intensive functions such as interface
protocols, application-specific functions, and proprietary custom IP. The
Embedded HardCopy Blocks offer customers faster time to market for their
designs while also reducing cost and power. For Altera, this innovation allows
the company to quickly create variant products and target specific market
segments.
Partial reconfiguration allows designers to reconfigure part of the FPGA while
other sections remain running. This is extremely important in systems where
uptime is critical because it allows designers to make updates or adjust
functionality without disrupting services. Lowering power and cost, partial
reconfiguration also improves effective logic density by removing the necessity
to place in the FPGA functions that do not operate simultaneously. Instead,
these functions can be stored in external memory and loaded as needed. This
reduces the size of the FPGA by allowing multiple applications on a single
FPGA, saving board space and reducing power.
To date, partial reconfiguration solutions have been time-intensive tasks that
required designers to know all of the intricate FPGA architecture details.
Altera is simplifying the partial reconfiguration process by building the
capability on top of the proven incremental compile design flow in its
Quartus(r) II design software.
Extending its leadership in embedded transceiver technology, Altera has
developed 28-Gbps embedded transceivers, which will also be implemented in
upcoming 28-nm FPGAs. These high-speed transceivers will enable customers to
implement next-generation designs such as 400G systems on a single chip without
the need for costly external components.
"Two years ago, Altera introduced the industry's first 40-nm FPGAs, and
continued delivering industry firsts such as embedded 11.3-Gbps transceivers,"
said John Daane, president, chairman and CEO of Altera. "As we move to the next
process node, these new innovations from Altera will take the industry beyond
the benefits of Moore's Law to solve bandwidth challenges while staying within
cost and power requirements."
About Altera
Altera programmable solutions enable system and semiconductor companies to
rapidly and cost-effectively innovate, differentiate and win in their markets.
Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
Follow Altera via Facebook, RSS and Twitter.
Altera, the Altera logo, and all other words that are identified as trademarks
are, unless noted otherwise, Registered, U.S. Patent and Trademark Office, and
the trademarks of Altera Corporation in the U.S. and other countries. All other
product or service names are the property of their respective holders.
This contains a forward-looking statement regarding the incorporation of new
innovations into upcoming 28 nm FPGAs that is made pursuant to the safe harbor
provisions of the Private Securities Litigation Reform Act of 1995. Investors
are cautioned that all forward-looking statements involve risks and
uncertainty, including without limitation the risk that future performance is
dependent on product development schedules, the design performance of software
and other tools, as well as the company's and third parties' development
technology and manufacture capabilities. Please refer to the company's
Securities and Exchange Commission filings, copies of which are available from
the company without charge.
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