[SI-LIST] Agenda, Asian IBIS Summit (Japan), September 14, 2007 - Agenda
- From: "Mirmak, Michael" <michael.mirmak@xxxxxxxxx>
- To: <ibis@xxxxxxx>, <ibis-users@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 7 Sep 2007 06:56:38 -0700
All,
We are pleased to announce the agenda for the Asian IBIS Summit
(Japan) meeting, to be held in Tokyo on September 14. Those interested
in attending are invited to register using the form and addresses below.
We look forward to a successful event.
Takeshi Watanabe
NEC Electronics Corp.
Michael Mirmak
Intel Corp.
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S U M M I T I N F O R M A T I O N
Time/Date: 8:30 - 16:00, Friday September 14, 2007
Location: JEITA Headquarters
3rd Fl., Mitsui Sumitomo Kaijo Bldg. Annex 11,
Kanda Surugadai 3-chome, Chiyoda-ku,
Tokyo 101-0062
JAPAN
http://www.jeita.or.jp/english/about/location/index.htm
Registration: FREE, send to both addresses below:
Name:
E-mail address:
Company:
Telephone:
Bob Ross, Teraspeed Consulting Group bob@xxxxxxxxxxxxx
Takeshi Watanabe, NEC Electronics Corp. takeshi.watanabe@xxxxxxxxx
Organizational Sponsors:
Japan Electronics and Information Technology Industries
Association (JEITA)
EIA IBIS Open Forum
Co-Sponsors: (in alphabetical order)
Agilent Technologies
ATE Service Corporation (Sigrity)
Cadence Design Systems
Cybernet Systems
IVIS (Signal Integrity Software (SiSoft))=20
Mentor Graphics Corporation
Zuken
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I B I S S U M M I T M E E T I N G A G E N D A
8:30 REFRESHMENTS & SIGN IN
- Vendor Tables Open
9:00 Meeting Welcome
Watanabe, Takashi (NEC Electronics Corp. and JEITA, Japan)
Mirmak, Michael (Intel Corporation, USA)
9:10 JEITA EDA Activity Overview
Watanabe, Takashi (NEC Electronics Corp. and JEITA, Japan)
9:25 IBIS Quality Activities Overview in JEITA EDA WG
Kondo, Yasumasa (Toshiba, Japan)
9:50 Validation for IBIS Models
Wang, Lance*, Zhang, XinJun**, and Yan, Benny**
(IO Methodology, *USA, **China)
[Presented by Wang, Lance (IO Methodology USA)]
10:20 IBIS Tree and Evolution Document Update
Ross, Bob (Teraspeed Consulting Group, USA)
10:30 BREAK (Refreshments)
10:45 JEITA Activity, IBIS Guide for the Japanese Engineer
Shoji, Kazuyoshi (Hitachi ULSI Systems, Japan)
11:10 Understanding and Using ICM Models
Meng, YuBao (Cadence Design Systems, China)
[Presented by Masuko, Yukio, Japan]
11:40 Study of the Interconnect Model
Ikeda, Hiroaki (Japan Aviation Electronic
Industries, Japan)
12:00 FREE BUFFET LUNCH (Hosted by Sponsors)
13:00 Issues Combining Buffer and Interconnect Models
Mirmak, Michael (Intel Corporation, USA)=20
13:30 Power Delivery System Design Automation
Xu, Tao (Sigrity, China)
[Presented by Chitwood, Sam (Sigrity, USA)]
14:00 IBIS-ATM Update: SerDes Modeling in IBIS
Westerhoff, Todd (Signal Integrity Software (SiSoft), USA
14:25 SerDes Modeling: IBIS-AMI Evaluation Toolkit
Westerhoff, Todd (Signal Integrity Software (SiSoft), USA)
14:35 IBIS AMI Model Developers Toolbox
Shah, Hemant (Cadence Design Systems, USA)
[Presented by Masuko, Yukio, Japan]
14:45 BREAK (Refreshments)
15:00 A Review of Existing Multi-Gbps Serial Channel Analysis
Methods and the Evolution of the Proposed ATM Algorithmic
Modeling Standard
Dodd, Ian*, Ward, Richard** and Gupta, Sanjeev* (*Agilent
Technologies, USA and **Texas Instruments, USA)
[Presented by Dodd, Ian, Agilent Technologies, USA)
15:30 An Overview of High-Speed Serial Bus Validation
Techniques
Muranyi, Arpad and Dmitriev-Zdorov, Vladimir
(Mentor Graphics Corporation, USA)
[Presented by Muranyi, Arpad, Mentor Graphics Corp., USA)]
16:00 Open Discussions
16:25 Concluding Items
16:30 END OF MEETING (POST-SUMMIT REFRESHMENTS)
=20
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