[SI-LIST] Advice for routing differential pair out of a BGA
- From: jhasson@xxxxxxxxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 30 Aug 2009 15:47:32 +0200
Hi,
We are working on a board hosting an FPGA in a 780 ball BGA package. We
are using the serdes of the FPGA at 2.5Gbit/s. The pinout of the BGA is
such that some of the serdes pins are on the 4th and 5th rows in the BGA.
We intend to use one layer of microvia (one on each side of the board)
with the BGA on the top layer.To output these signals we have two options
we are considering today :
go through a uvia to layer 2 then a via to layer n-1 then out of the BGA
area and to layer N when going to the DC blocking capacitor and stay
there.
go directly from layer top to layer n-1 without using uvias and no
backdrilling
Is any of these options preferable and for what reason ? In other words,
can the microvia be an issue ?
Best regards,
JF Hasson
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