[SI-LIST] Abt Layer StackUP
- From: chundi srikanth <chundis@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 21 Sep 2009 10:56:55 +0530
Hi All,
Can u just help me out in layer stack up. I will just describe abt our
critical signals.
Iam designing a board of 12 Layer which got both High-speed Digital and RF
signals of up to CPRI rate-4 i.e., 3.125Gbps.
We have several power supplies to cater the needs of the FPGA and other
digital and RF components. And high-speed clocks are also available @ 1GHz
rate. And we are having high-speed DACs & ADCs with LVDS interface. And the
DACs and ADCs are interfaced with Vertex-5 FPGAs. And we have signals of
High-sped SERDES interface for CPRI interface too. Iam very concerned about
my Board size its very compact with having all the high-speed signals. So
what are main concerns with high-speed LVDS signals? And can u just suggest
best stack up which i can proceed with?
Thanks in advance.
Regards
Sree
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