[SI-LIST] AW: VIA stubs
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 20 Aug 2012 15:21:52 +0000
Hi Knut,
no, you don't have to be concerned. Even with bad antipad design, your via will
resonate at very high frequencies (>15GHz) and that shouldn't affect your 6GBps
signal in any way. You might be able to see some additional coupling to nearby
vias, and maybe some EMC effects, depending on whats near the vias, but I
wouldn't be concerned at all, maybe alarmed.
To find out what's the maximum stub length your design can tolerate, you need a
3D simulation, as there are many parameters that effect the resonance
frequency, but in this case of a 1.1mm stub, even small variations will not
kill your performance.
The signal will in fact "see" the stub. There has been a nice paper at
Designcon a few years ago (sorry, I don't recall the year or title) about the
difference of 3D simulated vias versus using a capacitance in a circuit
simulator. The TDR looks similar in both cases, but reflection and group delay
differs a lot. Maybe Google helps you find this paper.
BR
Gert
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Knut Gabrielsen (kngabrie)
Gesendet: Montag, 20. August 2012 16:58
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] VIA stubs
Hello Experts!
I am involved in a design where we need to transfer ~6Gbit/s diff-signals
between a processor and an FPGA. If I route these signals as striplines inside
the PCB, there will be a stub on the (through-hole) VIA, stub-length ~1100um =
43mil.
My question to you all: Should I be concerned? At what frequencies will a VIA
stub seriously affect SI?
And - will the signal see the stub itself, or just "experience" the VIA as a
stray capacitance on the transmission line?
Rgds,
Knut
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