[SI-LIST] Re: AW: Re: DDR-II: SSTL_18 & ODT
- From: Bret Stott <bstott@xxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 14 Aug 2002 13:40:20 -0700
Hi SI-gurus,
Thanks for the responses. If I understand Hermann, it appears that a typical
bus topology is:
DRAM DRAM
| |
(55 ohm stub) (55 ohm stub)
| |
(RS=20) (RS=20)
| |
(drvr)--(40 ohm lead in trace)---(40 ohm)--
Is this correct?
Are there any series resistors at the memory controller? Is a class I or II
driver assumed for the M.C.?
I can see the AC matching between the 40 ohm lead-in and the
75||75 = 37.5 ohm DIMM pair. But what about the DC resistance VREF? This is
20+75 = 95 ohms. Won't this system take a few passes to reach it's final
value?
The 1 DIMM system is even more confusing to me. The 40 ohm lead-in looks into
a 75 ohm impedance and the DC resistance is 170 ohms. Perhaps I just need
to build a spice simulation to understand the above bus topology.
Thoughts?
Thanks,
-Bret
Quoting hermann.ruckerbauer@xxxxxxxxxxxx:
>
> Hi,
>
> two comments:
>
> Up to now there is no final SSTL18, but there will be a SSTL18 =
> eventually!
>
> And it is correct, that the ODT values are some compromise between =
> Power and
> SI. But there are some more thoughts.
>
> First the problem is, that (usually) read data sees different topology =
> then write=20
> data (expect e. g. a star bus topology). So optimization for read is =
> very often=20
> worse for write.=20
> In cas of ODT and DDRII the topology for a two slot system is some kind =
> of asymetric
> T bus. E. g. the LeadIn on Mobo is 40 Ohm and on the DIMM you do have a =
> 20 Ohm Stub
> resistor in series with a 55 Ohm trace. For the Write in a two slot =
> system, the data sees
> a 40 Ohm trace, and then 20 + 55 ohm in parallel with the second slot =
> (20 + 55 ohm).=20
> If you are calculating this one, the branch is not to bad matched.=20
> And for the 20 + 55 Ohm the 75 Ohm is not the worst termination for the =
> second slot.
>
> In case of a single Slot system the termination of DDRII is done on the =
> same slot, that is=20
> written to (of course, as there is only one slot poplated). To burn not =
> to much power, the
> termination is only half of the 2 Slot system. This can be done, as for =
> a single slot
> population the SI is not as bad as for the dual slot system.
> So this is one of the tradeoffs between SI and Power, that Gregory =
> mentioned=20
>
>
> regards
>
>
> Hermann
>
> -----Urspr=FCngliche Nachricht-----
> Von: pgregory [mailto:pgregory@xxxxxxxxxx]
> Gesendet am: Dienstag, 13. August 2002 23:38
> An: 'si-list@xxxxxxxxxxxxx'
> Betreff: [SI-LIST] Re: DDR-II: SSTL_18 & ODT
>
>
> JEDEC has two SSTL specs: SSTL_2 (2.5V) [JESD8-9B] and SSTL_3 (3.3V).
> There is no SSTL_1 or SSTL_18 JEDEC spec. =20
>
> The HSTL spec is a 1.5V spec [JESD8-6]. The industry has created a=20
> defacto standard for HSTL operating at 1.8V (see Micron RLDRAM and=20
> QDRII data sheets=20
> http://download.micron.com/pdf/datasheets/sram/MT54W1MH18B_4.pdf )
>
> On-die-termination has to balance many things including power and
> SI. The non-ideal termination is a compromise. See=20
> http://download.micron.com/pdf/technotes/TN4606.pdf for a look=20
> at some comparison values.
>
>
> -----Original Message-----
> From: Bret Stott [mailto:bstott@xxxxxxxxxxxxxxxx]
> Sent: Monday, August 12, 2002 12:35 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR-II: SSTL_18 & ODT
>
>
>
> Hi SI-gurus,
>
> I am a new member of this list and I have a few questions about DDR-II =
> that
> I=20
> was hoping someone could help me out with. Currently, I don't have =
> access
> to=20
> JEDEC so most of my information is from alternate sources such as the
> Samsung=20
> DDR-II spec.
>
> o Can anyone point me at a SSTL_18 specification?
>
> o Can someone help me understand the on-die-termination strategy for =
> DDR-II?
>
> Why are the values 75 & 150 Ohms? What electrical topology is being
> assumed?
>
> o My initial analysis suggests that it is possible to use class I =
> drivers
>
> for=20
> the address bus (5 load) and also for a point-to-point data bus. The =
> data
> bus=20
> may require some non-standard termination values though. Does anyone =
> have
> any=20
> information that supports of refutes this?
>
>
> Thanks in advance,
> -Bret
>
>
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----------------------------------------------------------------
Bret Stott phone: (408) 772-5028
Syano Designs fax: (408) 243-1850
771 Hilmar Street email: bstott@xxxxxxxxxxxxxxxx
Santa Clara, CA 95050 http://www.syanodesigns.com
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