Hmmm... I would have thought the very large loop area--with the ground
conductor being so far away--could present a big problem, as it dramatically
increases susceptibility to external magnetic fields, regardless of how high
the signal frequency is. It's not just internal crosstalk that you have to
worry about.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee Ritchey
Sent: Monday, November 30, 2015 11:47 AM
To: Gert.Havermann@xxxxxxxxxxx; istvan.novak@xxxxxxxxxxx; movax@xxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AW: Re: AW: Wiring Harnessing SI Question
Well put.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Havermann, Gert
Sent: Monday, November 30, 2015 12:58 AM
To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>; istvan.novak@xxxxxxxxxxx;
movax@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AW: Re: AW: Wiring Harnessing SI Question
Quote Lee Ritchey: "One must remember that the electromagnetic field
surrounding a conductor considers all other metal nearby partners, no matter
what their AC or DC names are and some of the return current will flow in each
of them"
And that is exactly what I meant when I said that the return path isn't the
problem, its Reference, because a return path is a closed path, but reference
can be anything that is just close enough to couple into. And in a loose wire
harness the reference to one single wire will change along the way.
BR
Gert
----------------------------------------
Absender ist HARTING KGaA; Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Bad Oeynhausen; Register-Nr.: HRB 8809; Vorsitzender des
Aufsichtsrats: Dipl.-Kfm. Jörg Selchow; persönlich haftende Gesellschafter:
Dipl.-Kfm. Dr.-Ing. E.h. Dietmar Harting, Philip F.W. Harting, Maresa
Harting-Hertz; HARTING WiMa AG (Luxemburg) & Co. KG, HARTING Beteiligungs GmbH
& Co. KG; Generalbevollmächtigte Gesellschafterin: Dipl.-Hdl. Margrit Harting
-----Ursprüngliche Nachricht-----
Von: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]
Gesendet: Samstag, 28. November 2015 02:06
An: istvan.novak@xxxxxxxxxxx; Havermann, Gert; movax@xxxxxxxxx;
si-list@xxxxxxxxxxxxx
Betreff: RE: [SI-LIST] Re: AW: Wiring Harnessing SI Question
One must remember that the electromagnetic field surrounding a conductor
considers all other metal nearby partners, no matter what their AC or DC names
are and some of the return current will flow in each of them.
Further, if the electromagnetic field is varying (AC) some energy will be
induced into each of them (crosstalk) no matter what their DC or AC name is.
The problem is much easier to understand and manage if you think in terms of
fields and waved instead of currents. Currents are an effect, not a cause.
The EM filed is the cause.
Lee
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Istvan Novak
Sent: Thursday, November 26, 2015 8:16 AM
To: Gert.Havermann@xxxxxxxxxxx; movax@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AW: Wiring Harnessing SI Question
I think return current vs signal reference is just two different viewpoints of
the same thing...
First I would verify the signal rise and fall times: in these days
low-frequency data transfer does not necessarily mean that the corresponding
edges will be proportionally slower. Though your situation looks quite
extreme, a first-cut check still would give you good guidance: if the round
trip delay through the entire signal path is less than ten percent of the rise
time, likely that reflection and termination (or the lack of) is not the cause.
Assuming that this is the case, you would not need 3D or distributed models,
rather you would need lumped LC matrices describing the coupling among the
wires. You could then use simple hand calculations or a circuit simulator to
find out the noise on a victim line.
Regards,
Istvan Novak
Oracle
On 11/26/2015 4:01 AM, Havermann, Gert wrote:
Don't think too much about Return currents, your Problem is signal reference.a
When conductors are floating free, then especially the clock signals will
couple into every conductor that is close enough to couple (Clock has the
highest frequency content especially with fast rising edges). Depending on
cable length and relative position clock will strongly couple into other
lines (Data or different Clocks). You should be able to see those using an
simple scope with high impedance Probes. The easiest way to improve your
system is to use either coaxial or paired Cable including a solid reference
(GND) or to use much thicker cable isolation (or different wire harnesses) to
add distance between the signal wire and other wires. In a multi wire Cable,
you can separate these wires by assigning wires optimally, but for free wire
harness that’s a problem.
BR
Gert
Besuchen Sie uns auf der SPS/IPC/DRIVES 2015 vom 24. bis 26. November 2015 in
Halle 10, Stand 140.
Entdecken Sie unsere Ideen und Lösungen zu Integrated Industry -
„HAII4YOU – HARTING Integrated Industry 4 You“.
http://www.HARTING.de/SPS
----------------------------------------
Absender ist HARTING KGaA; Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Bad Oeynhausen; Register-Nr.: HRB 8809; Vorsitzender
des Aufsichtsrats: Dipl.-Kfm. Jörg Selchow; persönlich haftende
Gesellschafter: Dipl.-Kfm. Dr.-Ing. E.h. Dietmar Harting, Philip F.W.
Harting, Maresa Harting-Hertz; HARTING WiMa AG (Luxemburg) & Co. KG,
HARTING Beteiligungs GmbH & Co. KG; Generalbevollmächtigte
Gesellschafterin: Dipl.-Hdl. Margrit Harting
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] Im Auftrag von Krunal Desai
Gesendet: Mittwoch, 25. November 2015 19:29
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Wiring Harnessing SI Question
HI all --
Hoping that list can shed some light on some wire harness related SI
questions at some very, very low speeds.
This list has done a good job teaching me about SI in general, and especially
the concept that while DC (i.e. power delivery) enjoys the path of least
resistance, the same is not true for AC signals (I think rule of thumb says
above 100kHz?).
We have a design where we have a 50-pin connector to our DUT on one end. This
goes to a Y-adapter which turns into 2x 32-pin MIL-STD circular connectors,
then a 6-8ft harness, and then our host / test equipment box. Earlier this
year, we decided to make one cable power, and one cable data -- logical,
right?
Recently though, we've observed severe SI issues when running two data
interfaces simultaneously (1MHz JTAG, and I2C) and this got me thinking, and
re-reading what we designed. Turns out that we were very thorough in our
power and data separation -- there are no grounds in the data harness at all!
This reminded me again of AC return currents and their wanting to minimize
loop area.
Here is my theory / gut feeling -- as the host box clocks out an edge
on lets say TCK, which is driven by a fairly "slow" driver (~15ns rise
time I think), at a frequency of 1MHz, it will leave the driver,
travel on a PCB trace, hop onto the harness, traverse the harness, hop
onto the DUT PCB and into the input device. Not to anthropomorphize
current too much, but at this point having made the long trip to the
DUT, he really wants to get home as fast as possible (and in as small
a loop area as possible). Unfortunately for him, the DC ground return
path is "far" away from the path he arrived on (the two cables kind of
flop around near each other), so he's going to take some path back in
the signal harness -- which could unfortunately be some output driver
that happens to be at '0', or some other data line. This isn't a
ribbon harness, so the conductors just float around in space
constrained only by braid. I think on my scope I can see odd /
increased noise when certain lines
re low -- does that low impedance path to GND encourage return current to
flow on that line? If I idle all I2C traffic, I get no errors on JTAG
whatsoever, but when I2C traffic begins to occur, my JTAG transaction quickly
become corrupted.
This is the majority case; I've also observed the inverse behavior where JTAG
squashes I2C.
Am I on the right track here? Or should I be looking more for reflections /
impedance mismatches? This is not a fast interface overall -- the edge rates
aren't ultra-fast and I2C is an open-drain, slow bus! (I have heard stories
of people tuning the VOL strength of their I2C devices before).
Additionally, I swear I remember reading somewhere an article (or maybe it
was on the list) for a good rule of thumb on how many return conductors to
provide for a given signal harness with n signal conductors -- does anyone
recall this?
Thanks! I'm hoping to work out / test this problem over Thanksgiving
-- it's a frustrating one, but those are also the ones that give you the best
feeling when you defeat them.
KD
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
