[SI-LIST] Re: AW: DDR Eye diagrams
- From: ji-wei_du@xxxxxxxxxxx
- To: hermann.ruckerbauer@xxxxxxxxxxxx
- Date: Wed, 28 Jul 2004 18:06:37 +0800
Hello Hermann :
It's very hard to explain the method I described using text only . =
And attachment is not allowed in this forum , so , I will send you some =
screenshots to explain the method in details in a separate message . =
I did not mention the scopes I am using or any information related to =
the scopes. The reason is "SI forum" is a good place to share =
experience and knowledge , not to sell any products (BTW , I am not a =
sales). =20
=20
Based on your discription , the method I am using is just based on =
the relation to a sorceSync signal (e.g. DQS). Yes , there is no such =
solution in the past .=20
=20
I will send you the screenshots and even powerpoint file , setup =
files ,test procedure... tomorrow . I am very glad to share my =
idea/product with you , DDR makers . ( You know , any engineer want to =
get feedback on the products he develops ,although it's already =
verified. I like to do some R&D job even I am not a R&D engineer .)
Another benifit of this test software is you do not need to worry =
about the Hi-Z status of DQS and DQ which bring problems with reliable =
trigger .
Regards
Jiwei Du
-----Original Message-----
From: hermann.ruckerbauer@xxxxxxxxxxxx
[mailto:hermann.ruckerbauer@xxxxxxxxxxxx]
Sent: 2004=C4=EA7=D4=C228=C8=D5 17:39
To: ji-wei_du@xxxxxxxxxxx
Cc: david.novak@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: AW: [SI-LIST] AW: DDR Eye diagrams
Hi,
thanks Jiwei Du, for your answer,
here some comments:
David mentioned, that he uses some serial termination. This should make =
sure that he is getting different levels between write and read.
The trigger jitter that you mentione is one of the reasons, why I =
suggest a dual event trigger: enable the trigger when expecting a Read =
or write, and fire the trigger with a defined clock or DQ edge (with a =
optimal trigger level at midpoint).
I didn't mention this, but I expected the same concept for the logic =
triggering, enable the trigger by a logic event, and fire the real =
trigger by a well defined clock/DQS edge.
Your test method looks really intersting, also I do not fully =
understand in the moment ...
My understanding is, that you are taking a deep memory single =
aquisition, and do some additional filtering of the data (similar like =
e. g. Tek Jitter3/RTE (sorry I do not know the way agilent scopes are =
doing this ;-) ) would do).=20
In this case you would need to take two waveforms (DQS/CLK and DQ) and =
calculate their relation only for Writes or Reads.
Is this understanding correct ?
Can you share any of your screenshots or even the program that you are =
using ?
Btw. I was always looking for a software that can do some sourceSync =
based calculation. So far every option for a scope to e. g. make =
dataeyes is using communication based concepts (E.g. CDR with any PLL), =
but none can make a dataeye based on the relation to a sorceSync signal =
(e.g. DQS). And when triggering on DQS the scope triggerjitter is =
always included in the measurment.
If anybody knows wa nice way to create nice source sync dataeyes or =
measurements I would be very thankfull to get this information!!!!
thanks and regards
Hermann
-----Urspr=A8=B9ngliche Nachricht-----
Von: ji-wei_du@xxxxxxxxxxx [mailto:ji-wei_du@xxxxxxxxxxx]=20
Gesendet: Mittwoch, 28. Juli 2004 10:41
An: Ruckerbauer Hermann (MP PDT PD MDS); david.novak@xxxxxxxxxxx; =
si-list@xxxxxxxxxxxxx
Betreff: RE: [SI-LIST] AW: DDR Eye diagrams
Hi Hermann :=20
I once used the same method to do test for DDRI/II DIMM from =
different vendors .=20
It's not 100% true that write and reads are different in high and low =
levels . Especially at DIMM chip pins side , the amplitude of =
read/write are very similar . It's ture that write and reads are =
different at controller side or near controller side (eg. gold fingers =
at a DIMM) . I verified this with the simulation software I am using ( =
I can share the simulation result with you if you want) . Please note =
that trigger jitter is much bigger when you set the trigger level to =
higher voltage . Say , the scope trigger jitter is 10ps at middle level =
, it may be 50 ps at high level . And the measurement result for " =
tAC , tDQSCK, tDQSQ,tDSS,tDSH " are not accurate , because the =
reference point ( trigger point) is not exactly the point we want .=20
Regarding the logic trigger mentioned by you , I tried that before , =
and found that WE~ and RAS~ can not 100% gurantee to isolate read or =
write cycle reliably , and you still can not remove trigger jitter (not =
only for one channel ,but or the jitter accross all of the channels you =
are using for trigger ) .
=20
Based on the above exprience , I develop a special program/method to =
improve the test , after serveral round of modification , it seems =
perfect to me now ( I like to be challeged by others with technical =
questions , please correct if you think I am wrong) : =20
1. As you said , if I test the signals near the controller side , then =
the reads and write are different in high and low levels . Step 1 : =
We define which cycles you want to measure by defining the high and low =
levels and middle level (reference voltage point) for the signal under =
test . =20
Step 2 : Folding the edge of DQS or CLK (depends what parameters you =
are measuring) based on the defintion of step 1 . You will just get =
the eye-diagram of write cycles and bit by bit information is included =
in the eye . There is no trigger jitter and dead time between adjacent =
UIs . =20
=20
To find the worst case , you can set the trigger condition to =
whatever you want . For example , with light loading , worst case of =
SSN will probably happen near the DDR pins , DQ with long "1" may be =
crosstalked by rising edge of DQS . To find it , you can set the =
scope trigger on long "1" . Please note that the waveform update =
rate of RT scopes at 20Gsa/s per channel is usually not fast . With =
this method , you can get 10K cycles of clock information at least by =
one acquistion .=20
=20
I have many screenshot to compare this method with the traditional =
method . =20
=20
2. Regarding triggering on the write pre-amble I mentioned in the last =
message , you can use it although you can not guarantee it's valid for =
all the cases . To use this method , you need to minimize the trigger =
jitter by using a special software depends on which scope you are using =
.=20
As a conclusion , the method I mentioned in 1 can 100% guarantee the =
measurement for all cases and get the result without trigger jitter , =
without dead time . And decrease the test time dramatically in terms =
finding worst case . =20
The above method can be used with any scopes , although I just finish =
the verification with one type of scope .=20
Regards
Jiwei Du
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx =
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of =
hermann.ruckerbauer@xxxxxxxxxxxx
Sent: 2004=C4=EA7=D4=C228=C8=D5 15:09
To: david.novak@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AW: DDR Eye diagrams
Hi David,
there are two methods I usually use (but I not really like both of =
them)
Usually Write and Reads are different in high and low levels. So do an =
=3D A-B event trigger, e.g. you want to take a Write (measured at the =
DRAM), =3D connect a probe to another DQ channel at the controller and =
set the =3D level so high only a Write is catched. now you should have =
another probe =3D on the DQS at the DRAM to have a B event, and you can =
create an eye =3D timing referenced to the DQS for Writes at the DRAM =
(of course including =3D trigger jitter of the scope). If you use the =
clock as B event you should capture DQ and DQS for the =3D dataeye. =
Therefore you are missing the bit by bit correlation DQ to DQS =3D =
(assuming you are using a RT scope), but without this correlation you =
=3D might see the worst case that can happen over a long period of time =
more =3D likely!
Another way is to check the WE and RAS signal, and do some kind of =
logic =3D triggering.
regards
Hermann
-----Urspr=3DFCngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
=3D Im Auftrag von Novak David
Gesendet: Mittwoch, 28. Juli 2004 05:19
An: si-list
Betreff: [SI-LIST] DDR Eye diagrams
For measuring DDR eye diagrams, the best location to measure reads is =
at =3D =3D3D the memory controller and the best place to measure writes =
is at the =3D =3D3D DDR. For example, measuring reads at the DDR will =
show more =3D reflections =3D3D than actually seen by the memory =
controller (I should =3D mention that I =3D3D have only series =
termination).
This sounds simple, but I cannot think of a way to make the scope =3D3D =
=3D differentiate between reads and writes. You might suggest that I =
create =3D =3D3D a memory test which only does reads or only does =
writes. However, my =3D =3D3D worst case signals are when the entire =
system is running.
Can anyone tell me how to make the scope trigger only on reads or only =
=3D =3D3D on writes?
Thanks,
David
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