[SI-LIST] AW: AW: Clarification on PCIE2.0 Base Spec for Voltage Pk-Pk Measurement.
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: "Sharma, Rajeev" <rajeevsh@xxxxxxxxxxxxxxxx>, "rajeev.sharma4204@xxxxxxxxx" <rajeev.sharma4204@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 2 Jul 2014 13:45:22 +0000
Hi Rajeev,
I might have mixed this up with the PCIeGen3 Spec (I haven't checked).
BR
Gert
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Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339 Espelkamp;
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Dipl.-Ing. Torsten Ratzmann, Dipl.-Wirtschaftsing. Ralf Martin Klein
-----Ursprüngliche Nachricht-----
Von: Sharma, Rajeev [mailto:rajeevsh@xxxxxxxxxxxxxxxx]
Gesendet: Mittwoch, 2. Juli 2014 15:35
An: Havermann, Gert; rajeev.sharma4204@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Betreff: RE: [SI-LIST] AW: Clarification on PCIE2.0 Base Spec for Voltage Pk-Pk
Measurement.
Hi Gert,
Thanks for the response. But I didn't find any mention of this special Bit
pattern. In fact the spec says that the "The maximum value is calculated on a
per unit interval evaluation".
So it should be measured in the UI. What you are pointing out is probably for
the De-Emphasis measurement.
Rgds,
Rajeev
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Havermann, Gert
Sent: Wednesday, July 02, 2014 12:49 AM
To: rajeev.sharma4204@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AW: Clarification on PCIE2.0 Base Spec for Voltage Pk-Pk
Measurement.
The spec says that you should use a special Bit Pattern (8xHigh + 8xLow; or
64xHigh + 64xLow) to make sure that the ringing is settled. The p-p voltage is
then measured in the center of the ringing-free area. It is not measured at the
eye diagram.
BR
Gert
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339 Espelkamp;
Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB 8808;
Vertretungsberechtigte Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dipl.-Wirtschaftsing. Ralf Martin Klein
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Rajeev Sharma
Gesendet: Mittwoch, 2. Juli 2014 06:07
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Clarification on PCIE2.0 Base Spec for Voltage Pk-Pk
Measurement.
I need some clarification for PCIe 2.0 Base Spec Voltage Pk-Pk Measurement
Method.
As per the PCIe Gen2 Base Spec, the differential p-p is defined as below(for
both 5Gbps and 2.5Gbps data rate).
Vtx-diff-pp = 2*|Vp - Vn| and should be within 0.8v to 1.2v
Vp/Vn are single Ended Voltages.
I have the following questions on this
1)Each UI High/low level can have noise riding over it. In such a case, where
is this p-p measured? Is it measured at the center of the UI? Or it can be
measured at any point of the UI where p-p is minimum or Maximum?
2)If this p-p value is captured for million UIs, we will have a set of
Min/Mean/Max value. What this spec corresponds to? Does it correspond to Min or
Mean Value?
The spec doesn;t give any clarity about these questions.
Thanks for your response.
Rajeev
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- » [SI-LIST] AW: AW: Clarification on PCIE2.0 Base Spec for Voltage Pk-Pk Measurement. - Havermann, Gert
