[SI-LIST] Re: 8-Layer asymmetrical Stackup
- From: Michael Greim <mgreim001@xxxxxxxxx>
- To: Embedded <hw_si@xxxxxxxxxxxxxx>
- Date: Mon, 28 Sep 2009 07:26:22 -0500
Hi,
I am first curious about what are all these "standard" form
factors with a 1mm board thickness. Sure that there was
a logical reason, but 1mm would not have been my first thought,
or second or third, for a mass production standard, that would
support any amount of significant power or routing density.
Ok, You need to be concerned with bow and flex, especially
if you are planning on putting BGAs down. Around the core of
the board, look for copper weight balance. When routing is completed,
consider copper fills on the signal layers for copper balance throughout
(3D).
Stay tightly coupled with your fab vendor. What you propose is
manufacturable, but at this 5000 foot level with no other info, it is
just as easily designed to never be or with very low yield.
Get an understanding of the relevant problems and then you
will be able to come up with thought out solutions. Proactive
approaches to problem solving will often times yield better
results than reactive methods. Simply shooting from the hip,
you may have just a good a likely hood of hitting your target,
as hitting, well, almost anything but it.
-Mike.
On Mon, Sep 28, 2009 at 4:09 AM, Embedded <hw_si@xxxxxxxxxxxxxx> wrote:
> Dear Experts,
> In our dsign,we need minimum 5-signal layers including top and bottom
> layers.
> I can use blind via from L1 to L2 only. The blind via from L1 to L3 is not
> allowed.
> So we have to assign signal layers adjacent to top and bottom layer.
>
> So considering all these constraints,I am planning to use the following
> 8-Layer stackup.
>
> Stackup
> --------
> L1 --- Top (Signal/ Component)
> L2 --- Signal
> L3 --- Plane (VCC1)
> L4 --- Signal
> L5 --- Plane (GND)
> L6 --- Plane (VCC2)
> L7 --- Signal
> L8 --- Bottom (Signal / Component)
>
> The board thickness is 1mm. This stackup is not symmetrical. The Layer L4
> and L5 are unbalanced.
>
> We would like to know that in this stackup will there be any issue like PCB
> Warpage and Yield in board proto and production build?
>
> Ans also let me know your feedbacks on the stackup.
>
> Thanks in Advance
> MR
>
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--
Best Regards,
Michael C. Greim
And all this science they don't understand
Is just my job six days a week.....
We will either find a way or make one -Hannibal
In the middle of every difficulty lies opportunity -Al Einstein
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