Check for extended idle periods before the error occurs. If the recovery PLL is
trying to lock to data and not it's own reference and the data goes idle for an
extended period of time, the Rx PLL could be drifting and then fail to sample
correctly once real data starts up again.
Chris
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of bala
Sent: Tuesday, August 25, 2015 11:21 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] 10G SERDES issue
Hi All,
We have 10G SERDES channel between ASIC(MAC switch) and phy and there is no
issues if we initialize the system once and run the traffic .If we reinitialize
the system at particular interval ASIC throws an error and the link is not up.
There is no issue till PMA SERDES of ASIC.
We measured reference clock and it’s clean and jitter, phase noise are
within the spec .We measured data eye(internal eye after EQ block) in passing
and failing condition and both looks good.
What could be a reason for this failure?
1. PLL loop bandwidth
2.Recovered clocks are not meeting the jitter tolerance?
3. Anything to do with Consecutive identical digits
4. Anything to do with phase aligner and sampling point
Regards
bala
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